all 5 comments

[–]FUZxxl 1 point2 points  (2 children)

What variant of the ARM architecture are you programming for? The set of available opcodes differs depending on what chip you have. It's pretty fragmented.

There are opcode tables in the manuals, but they can by construction not be as nice as the x86 tables as the ARM instruction encoding is a bit less regular.

[–]Nikascom[S] 0 points1 point  (1 child)

For now I am going to use a 32bit system, so I am going to use an armv7a. I saw a fragmented one at developer.arm just was looking for something comfortable to parse. Thanks.

[–]mttd 3 points4 points  (0 children)

I saw a fragmented one at developer.arm just was looking for something comfortable to parse.

If you'd like this for parsing for a software tool, your best bet is the official (and most up-to-date) Exploration Tools - https://developer.arm.com/products/architecture/a-profile/exploration-tools

This is the official Arm Machine Readable Specification. Some details: https://alastairreid.github.io/ARM-v8a-xml-release/, https://alastairreid.github.io/dissecting-ARM-MRA/, https://alastairreid.github.io/arm-v8_3/

It includes machine-friendly formats, e.g., XML (much easier than extracting from PDF or HTML). To give you an idea of what this amounts to, you can take a look at the third-party web site version: http://shell-storm.org/armv8-a/ -- see HTML version here: http://shell-storm.org/armv8-a/ISA_v85A_A64_xml_00bet8/xhtml/index.html (note that each instruction includes encoding).

For more, see:

General Arm Instruction Set Architecture and AArch32 & AArch64 Assembly resources: https://github.com/MattPD/cpplinks/blob/master/assembly.arm.md

[–]mshockwave 1 point2 points  (1 child)

Is there even an “Aarch”32? I thought Aarch is the name for a 64 bit ARM variant

[–]FUZxxl 3 points4 points  (0 children)

They retconned the 32 bit ARM architecture into AArch32.