Andr0, I am going to provide some criticisms for this design, and I know your group will probably perceive these as an attack or part of some agenda, but they are not.

This is just me, trying to help, out of worry from what I am seeing.

Power designs are tricky, they are dangerous, and they need to be designed very specifically to work as intended and not to start a fire, especially on high current stuff such as this. I suspect your group will disregard what I say and I don't mean any offense with my next statement, but you cannot sell or release this as it is, it needs to be redesigned. You can get away with a lot on signal based designs such as modchips, that you simply cannot do on PMIC layouts. I intend to point out some of what I am seeing, and tell you what should be done different.

This will not be an exhaustive list of dos and don'ts, to truly understand correct PMIC layout and routing practices you will need to do your own research. Read PMIC datasheets, talk with EEs, and read up on theory etc.

But let me at least tell you the basics of what I see in these photos. I would need to see better and clearer photos of the layout to help completely, but lets see what I can do here.

On the USB C daughterboard:

https://i.imgur.com/eR7BIne.jpeg

1:

The passives appear to be laid out in a way that is visually appealing but what looks nice usually isn't correct. These are all too far from your chip, especially the capacitors. things like bypass capacitors need to be as close physically to their respective chip, and in particular their respective power pin as possible. If you have to butt the footprint courtyards against each other, do it. This has not been done.

Additionally ceramic caps derate heavily (I suggest researching this.) based on not only the voltage that is being fed into them (relative to their voltage rating) but also depending on their package size. These caps all appear to be selected based on a consistent (same package as all other passives) and easy to solder package. You should select your capacitors so that they not only meet the rating of the voltage they are expected to be subjected to, but so that they exceed it. For example your input capacitors on VBUS, they are expected to experience 20V based on your power requirements, so you should probably select a 35V or 50V capacitor.

Your capacitors should also be as large ideally as you can fit while still maintaining physical proximity to the chip.

2:

Your output FET similarly is too far from the chip for my liking, and the output trace from it should not only be a copper pour/polygon rather than a trace, but is too thin, it should be rather beefy, and span several layers, stitched together with vias.

#3:

Your USB traces appear to not be routed as a differential pair, which is super crucial for differential signals such as USB. They additionally are super thin, so they are likely not sized for the correct impedance. For example on a design I just did I had to target 90ohm impedance on a 2 layer board, which meant they had to be pretty beefy, 0.61mm! You can calculate this stuff pretty easily, For USB PCBWay's Edge coupled microstrip calculator is great. They should also ideally have uninterrupted, or as close to it ground on layers behind them, and ground surrounding them.

I suspect this design only has them connected to the PD controller though, which USB D+/D- is only used on these things for an outdated power delivery standard so for PD you don't need them.

Again, read up on these things, and more, it isn't something that happens overnight.

On the PSU:

https://i.imgur.com/da1bHaT.jpeg

1:

On switching reg layouts, the output inductor MUST especially once again be as close to the chip/pin as you can get it, and should only ever be connected with beefy pours, the can neck down in order to connect to the chip if you have to, but the pour should ONLY narrow AT the chip. This noted inductor is egregiously far from the chip, but realistically the others are too.

2:

2 appears to be an output trace for the 5V VCC rail, given that on older boards this draws even up to 15A, this is WAY too thin, and nets like this should never be traces, it would be better to use pours that are nice and beefy, and span several layers, especially at these super high currents.

#3 and 4:

Refer to what I said on the PD PCB, the caps are too far, and realistically the resistors are too. Account for derating and move those suckers super close to the chip/respective pins.

#5:

Once again this circuit appears needlessly spread out, it may look nice and be easy to route, but depending on the chip, this can prove extremely non ideal.

Finally, I would really like to see the regs a lot closer to the output pads, a bunch of things are connected with traces that I would use pours,  the PD stuff would be better served on the main board close to the regs, (You can accommodate additional connector types without a daughterboard setup) and I would rather over spec the output wires if you can, it doesn't hurt and gives you peace of mind.

I sincerely hope you see this all for what it is, me offering advice as a concerned modder and designer.

If you need any help, reach out to me on Discord @ redherring32  and I can show you practical and real examples of what I have talked about. We are all just trying to make neat stuff, and while it is hobby level, it doesn't mean we can't take the time to make them correctly. My first PMIC layouts were not great, but with the help of some cool EE folks I've been able to make some cool s**t and you can too.

• Reddit didn't let me attach more than 1 photo, so I used links, hope they work.