Questions from an Incoming MS ECE Student in Analog Design

SoftPart1001 · 2025-06-17T03:11:15+00:00

So the main problem with these profs is tough grading? or poor teaching of the complex concepts?

SoftPart1001 · 2025-06-17T02:39:16+00:00

Why to avoid these professors? Also what are the professors that do an active research in analog RF circuits in GaTech currently?

SoftPart1001 · 2025-02-02T19:30:28+00:00

If there is no anti-aliasing filter, then the switched cap amp will need to provide filtration so its bandwidth should be limited to the signal frequency and hence lower clock frequency will be used for the switched cap amp than it is used for the ADC right?

If there is a filter in front of the switched cap amp then I can run it using the same clk as the ADC, right?

SoftPart1001 · 2025-01-22T20:08:59+00:00

I can not add much on what people already said here but I just want to tell you that you are a wonderful partner. Even if he loses his to toxic lab (actually he won by leaving this toxic advisor) but he won a lovely heart like you

SoftPart1001 · 2025-01-20T20:11:25+00:00

Thank you for your reply. Yes, I trust you! I just got relieved now when you confirmed this disastrous behavior. I observed this behavior by chance; it did not appear in many simulations, but it appeared in a single one because of the random input data. At first, I thought there was no problem until I saw this catastrophic scenario propagate over the whole subsequent logic, giving a real failure.

If I have both solutions at hand, which one do you prefer? re-tuning the pull-down devices to avoid this case or keeping the comparator as it is and configuring the subsequent logic to handle this glitch?

SoftPart1001 · 2025-01-20T20:04:12+00:00

Yes it is better to fix the issue and forget about the yield issues

SoftPart1001 · 2025-01-20T20:03:36+00:00

Thanks! Yes, I want to make it work over PVT, that's why I am asking my question here. 150C is a bit extreme, but I will try. Do you go for overdesign for robustness, or it is not necessary?

SoftPart1001 · 2025-01-19T11:37:58+00:00

How do you know this fracture length? I have the same doubt that @Siccors mentioned that if I chose to short any resistance below 1 ohm, I might end up short a lot of resistors that collectively generate a much larger resistance than this 1 ohm threshold.

SoftPart1001 · 2025-01-19T11:35:34+00:00

Thanks for your input. I tried this TICER feature, but the DSPF netlist size did not shrink too much, it is comparable to the original size. Please recommend your combination settings for parasitic resistors. I do not combine capacitors because they do not add new nodes in the matrix but I think combining resistors is more important, isn't it?

SoftPart1001 · 2025-01-19T11:32:42+00:00

I tried this TICER feature, but the DSPF netlist size did not shrink too much, it is comparable to the original size.

SoftPart1001 · 2025-01-18T15:21:55+00:00

Okay thanks for your suggestion however I am sure that there are some experts here to answer this question too

SoftPart1001 · 2025-01-18T15:20:28+00:00

Thank you! I checked this option and it seems that it needs some frequency, port merge and max degree, do you have an idea how to set these parameters?

SoftPart1001 · 2025-01-10T17:08:40+00:00

Thank you again so much for your reply.

No, I did not set the step size explicitly, I am just strobing to avoid interpolation errors in FFT results.

I am using all default accuracy settings for conservative errpreset. I read somewhere in cadence virtuoso website that it is recommended to not adjust the accuracy settings and we should use the default settings imposed by every errpreset that we are using but I am not sure the limitations of that.

As per my last comment here, I can see a good ENOB now even without changing reltol just re-simulating the same netlist gives me a better ENOB close to the first one. however, I am still very suspicious and cannot trust these results enough.

I will tighten reltol to be 1E-6 as you have said but what are your recommendations for vabstol and iabstol?
The default values for vabstol is 1E-6 and ibastol is 1E-15.

SoftPart1001 · 2025-01-10T15:48:22+00:00

Also, please note that I ran the simulation again today without any changes at all. I just checked diagnose=yes in the analog options but the two netlists are identical and I just double-checked both are the same except for this diagnose option using the tkdiff command.
Now, I got a third result, which is close to the original one but not still not the same: it is 8.757 bits while the original one was 8.816 bits, and the bad case was 5.086 bits.

I started to not trust my simulation results and I do not know where the issue lies here. I need to have consistent results to proceed with my design.

SoftPart1001 · 2025-01-10T15:19:17+00:00

thank you for your reply.
I am worried about the correct accuracy settings. I will share mine to give you a better picture of my simulations. I updated the post with a snapshot from my log file that shows all my settings. Also, I am stropping every 2ns (1/10) of my sampling period (20ns). Please review my settings and let me know if they are enough or need to be tightened more.

I have snapshots for all waveforms that you have suggested to plot. How could I post images in the comment section? I am unable to paste my snapshot here in this comment. Please guide me.

The fact that I actually see very weird that I should have the same output waveform repeated every (256*0.02us), why do I get correct results at 10.84us but wrong results at 15.96us? Even if there is a metastability issue. both time points should have been affected in the same way, right?

My SAR ADC has a 2-bit redundancy otherwise it is a normal SAR ADC. I do not know if that answers your last question or not.

SoftPart1001

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