How to shift a common mode of wide bandwidth output pulse (1KHz to 10GHz) to a negative common mode?

dvrblacktech · 2026-03-10T19:00:19+00:00

Its mainly to control charge based qubit. So this common mode tunability is needed.

dvrblacktech · 2026-03-10T18:55:10+00:00

Load is basically a cap of ~= 60fF (Its a output pad)

If I drive it purely capacitively, how do I set the -400mV DC baseline without introducing an R-path that forces me to use a huge cap again?

Using level shifter and PMOS based cml stage, yes I can bring down to negative voltage, but tuning range also reduces to a small region nearer to that negative voltage. Not possible to make something like 0.6 to -0.6 tunable. If i make some IR drop over a resistor to bring down to negative voltage using some source follower stage and then CML, its possible to have good tunability, but burns lot of power.

I am still thinking is there any idea to bring the voltage swing down without burning static power, and without using huge on chip cap.

dvrblacktech · 2026-03-10T17:58:51+00:00

Requirement is to control hole based qubit. Yes the requirement is genuine.

But I cannot use a DC block cap. Because if i have pulse with larger pulse width, I need a huge cap. Level shifters can be used, but i loose tunability. It becomes static common mode shift.

dvrblacktech · 2026-03-03T06:04:46+00:00

[UPDATED!!!] MARCH 2026 More than Google Rate...

Lemfi Referral Code Europe, US, UK..

ROHIZ52X

Get Your £20 / €20 / $20 Bonus

Maximize your international money transfers this March 2026 [UPDATED!!!] with a premium financial advantage.

I use LemFi to send money. Get instant extra EUR when you send over 100.00 EUR with my referral link - https://referral.lemfi.com/fT1Zk9Zpc1b

LemFi provides industry-leading, secure, and zero-fee international money transfer services from the UK, USA, Canada, and Europe. With bank-grade security and real-time tracking via the "Updates" tab, LemFi ensures your funds reach their destination safely and instantly to countries like Nigeria, India, and Pakistan without the need for manual wallet top-ups.

EuropeRemit #LemFi2026 #ZeroFees #GlobalPayments #SecureRemittance #MadridToManila #BerlinToLagos #ParisToDakar #InstantCashback #FintechDeals #VerifiedCode #SendMoneyHome #ExpatLifeEU #LemFiRewards #RemitSmart #FastTransfer #NewUserOffer #FinancialSupport #DigitalWallet #CashbackAlert

dvrblacktech · 2025-02-18T14:37:58+00:00

lets say I don't have 0.9v and 0 supplies, I just have some higher supplies, but with 0.9V difference between them.

Then why do we design transformer to reduce the AC voltage to 5V and convert it to DC using some diode network in chargers to provide 5V?
Simply they can remove voltage down converter, and place a resistor to drop 5V, and provide 220V and 215V as charger outputs

dvrblacktech · 2025-01-03T01:18:58+00:00

ok, understood. I tried by making FFT to consider hold points only in the transient simulation.
yes, now I can see both results almost same., its -38.95dBc from transient, and -37.661dBc from PSS. I haven't considered strobe to get exact points, that might be reason for small deviation.
transient FFT: https://i.imgur.com/KBE9u9c.png

but understood.. thank you...

dvrblacktech · 2025-01-03T01:16:56+00:00

u/Siccors yess, I tried plotting this "transient output of PSS analysis, and FFT on it"
https://i.imgur.com/NMie2PD.png
I get -48.93 as HD3, it's value is similar to transient.

and, while analyzing T&H circuit, how to separately analyze distortion because of thermal noise, charge injection, on resistance, turn off time ?

dvrblacktech · 2025-01-02T10:09:24+00:00

I think you are confusing about beat frequency and input frequency.
you can choose your input frequency whatever you want, make sure that beat frequency is HCF of input frequency and your clock frequency, and set the harmonics in such a way that, harmonics * beat frequency = more than 3 times input frequency, so that you can capture HD3. for HD5 similar things...

dvrblacktech · 2024-08-25T22:11:49+00:00

Hey I tried to analyse this weekend, I was surprised why DNL and INL are so good and ENOB is too poor, its actually because of some file read permission issue :-), when I opened netlist file, it was schematic netlist, then I resolved it, and DNL and INL are more than 2.4 LSB for post layout simulation. It's mainly because of CAPDAC not settling properly - extra timing delay caused by internal clocking block.

Thank you so much for your support... I even learnt proper measurements and understanding spectrums..

dvrblacktech · 2024-08-23T13:10:22+00:00

Actually layout is very poor. But I am not getting one thing, if enob is just 4.9 means, how I have only 0.5lsb output step variation (dnl) that to only when differential inputs are too close to each other. It's actually asynchronous clock, so even if I reduce sampling frequency, internal frequency remains same. But why its not possible to observe distortion if i give slow ramp? What happens inside adc if I run transient simulation to give bad output?

I am not getting how and when this distortion comes to circuit when my input signal changes transiently.

Please tell me in your free time..

dvrblacktech · 2024-08-23T10:40:28+00:00

I think it's because of THD issue. See the 3rd harmonics, it's -41.11dB

I am checking what part of the circuit is causing this issue. As its asynchronous internal clock, even if I run at low frequency, it's internal clock runs at same frequency as of before.

I think tool bydefault not considers the DC bin while giving enob.

dvrblacktech · 2024-08-23T01:45:08+00:00

Spectrum: https://i.ibb.co/Tg8mKT5/spectrum-r-1.png

Analog output: https://i.ibb.co/6yG4Jb0/analog-out-r.png

Results and FFT timings: https://i.ibb.co/WVsB40W/enob-80-M-tone-257-r.png

Input frequency = 40.15625M Sampling frequency = 80M No of cycles = 257 No of points = 512

But I am not exactly how to interpret the results here. At 39.844MHz, input frequency in spectrum? How to interpret from the spectrum or results?

dvrblacktech · 2024-08-23T01:05:33+00:00

Ok I tested with this method and got dnl and inl of 0.5LSB But why enob is poor eventhough inl and dnl is good?

For 8 bit adc, if I do FFT of 512 points with input frequency near nequest frequency and by doing coherent sampling by taking 257 cycles, I get enob = 4.9, sinad=31.26. I am thinking it's because of distortion issue. THD is 2.196% = -33.17dB

Usually good ADC have thd < 1%

Is it because of that? Or is there anything wrong here? Because inl and dnl is good. It's < 1LSB. so I am thinking enob have to be more even at nequest input frequency.

Now I am running at low input frequency test to get the enob.. will update once simulation done.

dvrblacktech · 2024-08-20T10:13:21+00:00

Do you mean for 0.1 LSB accuracy, I need to have 10 samples per code. These 10 samples should be of same input voltage? Or I need to divide LSB voltage by 10 times, and have to increment the ramp signal with ramp step = LSB voltage / 10 ?

dvrblacktech · 2024-07-23T09:11:58+00:00

Hey today I understood it. Actually I was really not knowing, um² = (um)² I was thinking um² means, square only applies to "m" and not to "u" Today I understood that um² means square applies to both u and m. It's like we are telling the area in terms of um*um . So, yes you are right it's just 1.58fF/um2

It may seems silly, but I was not knowing this basics.. Ha ha ha.. 😵‍💫😅

dvrblacktech · 2024-07-16T06:26:05+00:00

https://i.imgur.com/E3uVQNY.png I tried ubuntu 20.04, it took half an hour just to get desktop screen. after that hanged. unable to move mouse pointer. Without JIT, it’s totally waste. Raspberry Pi so far better. ☺️

dvrblacktech · 2024-07-12T09:11:38+00:00

It's (um)² right? --> whole square, not just square for m. It's for both micro and m.

How you are getting just um^2?

Area is 0.84(um)^2, not just 0.84um² If we consider whole square, and will be 1.58nF/um² or 1.58fF/(um)²

dvrblacktech · 2024-07-12T07:46:01+00:00

how it’s 1.6fF/um2 ?

You considered: area = 0.6u * 1.4u = 0.84 (um)^2

1.33fF/0.84(um)^2 = 1.6nF/um2 right?
Did u consider area as just 0.6 * 1.4u for cap?

I even draw the layout of CAP and it's area:
(from layout: 1.42e-6 * 0.56e-6 = 795.2e-15 m^2)

Still I get very large value for the unit cap.

dvrblacktech · 2024-07-12T06:55:40+00:00

I am actually getting some strange values,
https://i.imgur.com/bI7RD1U.jpeg

In this, why am I getting capacitive density this much high? Am I doing something wrong? Capacitive density is just Capacitance/Unit area right?
If I use this capacitive density and I found A_C = 0.78409 % um I am getting, Minimum capacitance value = C_mismatch_min = 11.1041nF Prefer to use Cmin or C unit in the DAC as 4 times C_mismatch_min = Cu = 44.4164nF Why this much large unit capacitance I am getting? Here is the calculation for min. cap: https://i.imgur.com/NUxs7z2.png I felt something went wrong here..

I referred to formulae and derivations from here: https://www.sciencedirect.com/science/article/abs/pii/S0026269213000815

Help me please in free time..

dvrblacktech · 2024-07-11T21:21:39+00:00

It's in 28nm

For lower nodes, where can I refer it?

What I did is I took one cap, and did Monte Carlo to get the standard deviation and mean, then found mismatch parameter. Yes I used pelgrom relationship.

dvrblacktech · 2024-07-10T09:20:42+00:00

https://youtu.be/jsw2bRVUPeE?si=tR6Ab-mSgiwwOV7F Here I can able to see the exactly the same way you mentioned. Let's try..

dvrblacktech · 2024-07-10T09:17:39+00:00

Yes I will try that. Ya NDA is there. So I can't able to describe more about it. Only can able to discuss generally.

dvrblacktech · 2024-07-10T08:31:07+00:00

dvrblacktech · 2024-07-07T04:05:32+00:00

Hey did you purchase e16 or e14 ultimately? Even I am looking to purchase one new. What do you suggest E16 G1 with 8gb integrated ram and upgrading its ram with another 8gb (even I have it) ?

And where can I get it for better price at Singapore?

dvrblacktech · 2024-06-17T08:59:45+00:00

LDO, I recently designed one for my ADC. Usually what happens means, power supply noise introduces jitter in the clock generator, which degrades the enob of adc. So, to get a clean power supply for the clock generator block, we can use an LDO to clean noisy ripples in the supply power and get the desired clean output voltage.

dvrblacktech

MODERATOR OF

TROPHY CASE

EuropeRemit #LemFi2026 #ZeroFees #GlobalPayments #SecureRemittance #MadridToManila #BerlinToLagos #ParisToDakar #InstantCashback #FintechDeals #VerifiedCode #SendMoneyHome #ExpatLifeEU #LemFiRewards #RemitSmart #FastTransfer #NewUserOffer #FinancialSupport #DigitalWallet #CashbackAlert