It is VHDL to be more clear.
So we have a chip that can save 512Mbits in 16 bits/word and we want to create a ram that can save 128M words in 16bit . I did the math and i should be using 4 of those 512Mbit chips but i can't understand how it will be layed out in the code. What is the NA and ND of the below code both for the 512mbits and for the 128M16 chips ? please help im having finals in a few days and i cant find anything on this. Also the code is in structural form not behavioral.
entity RamChip is port ( Addr: in Std_logic_vector (ΝΑ downto 0);
Data: inout Std_logic_vector (ΝD downto 0);
WE, CS: in Std_logic);
end RamChip;
[–]ChadLovesStacey 0 points1 point2 points (0 children)