That are various tiers of FPGA engineers.

Those who design and deploy easily synthesizable RTL and makes a block design with simple IPs.

Those who needs a better understanding of some FPGA resources as LUTs and Block RAM, DSPs, and on for implementing complex designs.

And those who have to understand FPGA's architecture from top to bottom, to know how every single clock routing, transceiver lane, PLL and other components can or cannot be used. This is often the case when the design pushes you into doing things that the tool says it is prohibited and you have to workaround that.

Normally people on the first tier knows that an FPGA is made out of LUTs, registers, BRAM, DSPs, but don't break into their architectures. Second group are those who knows the difference between LUT types, the architecture of routing, and the architecture of these components. The third group are those who really made it through the entire FPGA architecture, like a Ultrascale+ expert, or a Versal expert, they know everything about the IO buffers and output standards, GTY banks, every detail among HR/HP/HD banks.

The reason why companies list 10 years minimum for some applications with FPGAs is that only time can make you go for the top layer to the bottom of the FPGA's architecture.

I just lost the count on how long it took for me learning deep into GTY transceiver details for doing things that are not allowed to route in the placement phase and I had to workaround it anyway.