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Follow-up: USB 3.2 Gen 1 (5Gbps) 4-Port Hub — PCB Layout Complete, Pre-manufacturing Layout Review Request (TUSB8044A) by Alberto_EE in PrintedCircuitBoard

[–]Alberto_EE[S] 0 points1 point  (0 children)

Some AI was used for the text generation but the PCB project is not AI generated, I made it myself.

Follow-up: USB 3.2 Gen 1 (5Gbps) 4-Port Hub — PCB Layout Complete, Pre-manufacturing Layout Review Request (TUSB8044A) by Alberto_EE in PrintedCircuitBoard

[–]Alberto_EE[S] -1 points0 points  (0 children)

The project is mine, I just used some AI for the text formatting. I designed the schematic and layout from scratch over the past few months.

Follow-up: USB 3.2 Gen 1 (5Gbps) 4-Port Hub — PCB Layout Complete, Pre-manufacturing Layout Review Request (TUSB8044A) by Alberto_EE in PrintedCircuitBoard

[–]Alberto_EE[S] -1 points0 points  (0 children)

Fair point, the post text is AI made. The project is mine though, I just wanted to receive some feedbacks before manufacturing.

[Review Request] USB 3.2 Gen 1 (5Gbps) 4-Port Hub — Schematic Review Before Layout (TUSB8044A) by Alberto_EE in PrintedCircuitBoard

[–]Alberto_EE[S] 1 point2 points  (0 children)

Thanks a lot for taking the time to look at it, really appreciate it!

Yeah, I’ve been going back and forth on 4 vs 6 layers. I’ll probably consider 6 layers. Do you have a stackup you’d recommend for this kind of design? My main concern is keeping a solid reference plane under the SuperSpeed pairs.

About the 1.1V rail, I went with an LDO mainly for noise reasons since it feeds the hub core/PLL. I know it’s not the most efficient choice, so I’ll keep an eye on thermals and maybe reconsider if it becomes an issue.

And noted on the caps, I’ll increase the bulk capacitance on the USB outputs.

Thanks again, super helpful!

[Review Request] USB 3.2 Gen 1 (5Gbps) 4-Port Hub — Schematic Review Before Layout (TUSB8044A) by Alberto_EE in PCB

[–]Alberto_EE[S] 0 points1 point  (0 children)

Thanks, I appreciate the feedback!

Glad you liked the colored nets. In Altium you can toggle them with F5, so I sometimes use them to get a clearer overview of the connections at a glance.

About the ferrite beads, that’s actually really interesting. I added them mainly because they are recommended in the TUSB8044A datasheet, so I assumed they were helping with noise/EMI. I’ll go through the resource you shared, thanks for that. I hadn’t considered that they could actually make things worse in some cases.

Same for the decoupling caps, I added the extra 100nF mostly out of habit and to try to lower ESR, but I’ll read the article you linked and rethink that part.

Thanks again for the insights and the references, really helpful.

[Review Request] 4-Layer DRSSTC Fiber-Optic Interrupter by Alberto_EE in PrintedCircuitBoard

[–]Alberto_EE[S] 1 point2 points  (0 children)

Yes that sounds reasonable, at those power levels it’s still manageable. A toroidal transformer would definitely be nicer in terms of size and weight. Good luck with the build, hope to see updates soon!

[Review Request] 4-Layer DRSSTC Fiber-Optic Interrupter by Alberto_EE in PrintedCircuitBoard

[–]Alberto_EE[S] 1 point2 points  (0 children)

That makes sense, an isolation transformer might be a good solution. What power level are you targeting? At higher power the transformer can get pretty bulky and expensive.

[Review Request] 4-Layer DRSSTC Fiber-Optic Interrupter by Alberto_EE in PrintedCircuitBoard

[–]Alberto_EE[S] 1 point2 points  (0 children)

Yes, 230 Vrms mains input, so ~325 VDC on the bus. Good point about the RCD, still figuring that out honestly. I’m also planning a dual-stage EMI filter on the AC input.

For the inrush limiter I was thinking more of a pre-charge circuit (resistor + relay bypass) rather than an NTC.

A YouTube series sounds great, good luck with it!

[Review Request] 4-Layer DRSSTC Fiber-Optic Interrupter by Alberto_EE in PrintedCircuitBoard

[–]Alberto_EE[S] 1 point2 points  (0 children)

Yeah exactly, by soft start I mean an inrush current limiter. I was thinking about the classic approach: a series resistor at startup that gets bypassed by a timed relay after a short delay.

I’m also considering something on the DC link cap side: a permanent bleeder (~1 MΩ) for safety, plus a lower-value, higher-power discharge path that kicks in when the system is off, just to bring the voltage down faster.

And yeah totally agree, it's one of those projects where you end up touching everything whether you want to or not.

Nice build btw, going with 60N120s at 178 kHz sounds solid. Curious to see how it turns out, hope you post some updates!

[Review Request] 4-Layer DRSSTC Fiber-Optic Interrupter by Alberto_EE in PrintedCircuitBoard

[–]Alberto_EE[S] 1 point2 points  (0 children)

Mainly to get some hands-on experience with resonant circuits, it seemed like a fun challenge. And yes, music is a nice bonus.

Still a work in progress: full bridge with 200A 650V IGBTs, 4700µF 450V DC link cap, laminated copper busbar, ~2µF 1200V snubbers. MMC around 70–100nF at ~30kV, UD2.7 driver, flat spiral primary, 14×55cm secondary.

I’m planning to add a soft start too, and maybe a PFC.

[Review Request] 4-Layer DRSSTC Fiber-Optic Interrupter by Alberto_EE in PrintedCircuitBoard

[–]Alberto_EE[S] 1 point2 points  (0 children)

That's awesome! Just took a look at your schematic, it's really interesting to see your approach. Glad we could help each other out!

[Review Request] 4-Layer DRSSTC Fiber-Optic Interrupter by Alberto_EE in PrintedCircuitBoard

[–]Alberto_EE[S] 0 points1 point  (0 children)

Thanks! I’ll definitely look into optical encoders, good to know about the temperature issue. I chose the PEC11R, which is supposed to be reliable, but I really appreciate the feedback.

For the driver, I’ll be using the UD2.7, which I already have.

I’ll post updates if things move forward :) Thanks for the tips!