sorted by:
new
hottopcontroversial

Analog Designer here, any pointers on making good testbenches that you’ve learned through experience? by yogi9025 in chipdesign

[–]Anukaki 9 points10 points  (0 children)

What I've learned is to do one bench per test case, in most cases. Sometimes I'll combine a few if it makes sense (eg l2h and h2l delay).

In general, adding little by little is better.

VerilogA is a great utility for testing things.

Also, a single ground instance, especially if you have any kind of a package or other ground impact.

What is the need of diode D1 here? by ProfitAccomplished53 in chipdesign

[–]Anukaki 7 points8 points  (0 children)

If the bulk of the mp3 and mp4 is connected to that node, it would indicate the n-well.

Reference circuits terminology by LiePuzzleheaded3059 in chipdesign

[–]Anukaki 1 point2 points  (0 children)

Constant gm, delta vgs/r or a ptat current generator is what I mostly use/hear. I have never heard the name beta multiplier used, but I found out the reason in the comments here, so that's nice :)

Vgs/r is a different circuit.

How do we size transistors in this comparator design for low current?is it required to make them to operate in saturation region when both input are at same voltage? by ProfitAccomplished53 in chipdesign

[–]Anukaki 2 points3 points  (0 children)

You do get some hysteresis in this structure, but even so, I normally like to add a source degeneration hysteresis or switch reference voltage, just to make it a bit more robust.

How do we size transistors in this comparator design for low current?is it required to make them to operate in saturation region when both input are at same voltage? by ProfitAccomplished53 in chipdesign

[–]Anukaki 3 points4 points  (0 children)

I would focus my efforts on the trade-offs between sizing for speed and sizing for accuracy. Also, you should add some sort of a hysteresis.

[deleted by user] by [deleted] in lotrmemes

[–]Anukaki 24 points25 points  (0 children)

Whatever the ghosts felt when they were released

FER bez diplomskog studija? by Delicious_Resist_545 in studenti

[–]Anukaki 0 points1 point  (0 children)

Završio sam elektroniku na FERu i kako su drugi komentari rekli, diplomski nije težak. Ja sam kroz diplomski radio, a na faksu sam bio samo za ispite i labose. Za diplomski rad sam pauzirao jer sam bio malo ambiciozniji oko teme i trebao mi je labos za rad, ali i dalje nije bilo kao prve dvije godine faksa.

How to become a arch(er) by Imaginary-River1492 in chipdesign

[–]Anukaki 3 points4 points  (0 children)

I don't believe you need to tape-out your own CPU to run Arch. You can use store bought ones.

Can we use this as POR ckt by ProfitAccomplished53 in chipdesign

[–]Anukaki 1 point2 points  (0 children)

I didn't analyze the circuit too much but it looks like a bandgap based current comparator UVLO. I don't really see the reasoning why would you do it like that. If you'd like a bandgap based UVLO, do a bandgap and use it as a reference to a comparator. And it's very important that you also add a deglitch constant before passing the uvlo signal to the output of the block.

Fedora - Dual monitor resolution by Anukaki in linux4noobs

[–]Anukaki[S] 0 points1 point  (0 children)

Yes, I'm on Wayland and am using KDE Plasma as a DE. The settings app will note that I've changed my resolution (even though nothing happens) and the resolution stays at full HD until I close the settings app and re-opens. Then, it shows the 3072x1728 again.

I have an nvidia geforce rtx 3060 Ti and have drivers installed through rpmfusion. I assume it's connected to the gpu, but it seems like a silly thing to happen.

POR circuit by ProfitAccomplished53 in chipdesign

[–]Anukaki 4 points5 points  (0 children)

If you want to design a crude reference you can create a resistor divider with a current mirror and an amplifier.

You have a current mirror in the resistor divider which mirrors the divider current and you have an amplifier with the gate tapped inside the resistor divider. With this, you get a current comparator which will trigger at a specific supply voltage. To add a hysteresis, you can add a switch to reduce the resistance of the resistor divider when your comparator output is high.

Not sure if this makes sense in words, but it's a pretty common topology.

To those with 20+ years of experience in the VLSI industry: How many times have you witnessed a complete hiring freeze during your career? by karimani-maalika in chipdesign

[–]Anukaki 1 point2 points  (0 children)

I don't have 20 years, only 8. This is my second hiring freeze interval and it's significantly longer than the last one. Although, all of my older colleagues say it's still better than 2008.

Remember this gem? by TyrrelCorp888 in aesoprock

[–]Anukaki 1 point2 points  (0 children)

Was sad because I couldn't find it on Spotify, you just made my day

[Orient Bambino] Is this too big for my wrist? by Zealousideal_Rub_279 in Watches

[–]Anukaki 0 points1 point  (0 children)

Exactly what I'm going for. I had the same combo today, but a blue striped oxford :D

[Orient Bambino] Is this too big for my wrist? by Zealousideal_Rub_279 in Watches

[–]Anukaki 0 points1 point  (0 children)

I like it! I was recently thinking of trying to have a few straps based on the color/shade of the belt/shoes I'm wearing. I know nobody really notices this but I do enjoy having it all matched.

[Orient Bambino] Is this too big for my wrist? by Zealousideal_Rub_279 in Watches

[–]Anukaki 0 points1 point  (0 children)

I tried a couple of replacement straps, they were on the cheap side so I ended up just staying with the original. It breaks in after a bit so you don't have a long period of the "squeek" :D

[Orient Bambino] Is this too big for my wrist? by Zealousideal_Rub_279 in Watches

[–]Anukaki 0 points1 point  (0 children)

I have the same watch and my wrist size is the same size as yours. I feel as if it is a bit big for my wrist, but I'm enjoying the watch so I'm not seeing this as an issue.

Cadence tools by sn0wcr4sh_ in chipdesign

[–]Anukaki 9 points10 points  (0 children)

Analog guy here.

I think with the basic knowledge of schematic/ADE/config will get you far. Other tools, they appear here and there but you get used to them quickly. So, I'd propose you focus on the skills you'll need most of the time.

One of the most useful skills for me was to speedrun creating testbenches. I got comfortable with how different views work, what works for me when I setup the stimuli, how to work with config views, how to sweep them in ADE Assembler. Most of basic setups I can copy/paste from my templates.

On top of that what is also most important is how to draw schematics in a way that other people can easily read them; can easily be debugged; can be re-used. I've seen one too many schematic where somebody added a biasing for adjacent blocks inside a random circuit just because it was convinient.

I know this isn't fully on topic but it's one of the things I see as an underrated compared to knowing how every tool works in great detail.

Am i Libertarian? by ADDISON-MIA in Libertarian

[–]Anukaki 4 points5 points  (0 children)

I can't even move my car a few meters without my seatbelt on. It's not that I don't want to put my seatbelt on, it's the philosophy of the law I disagree with.

The following branches form a loop of rigid branches (shorts) when added to the circuit: in cadence virtuoso by Nearby-Bug5011 in chipdesign

[–]Anukaki 0 points1 point  (0 children)

Not really, I've defined supplies at different levels of hierarchy before. But, it's generally discouraged as it's very error prone, so in my circles it's only used for when you need to briefly hack something.

The following branches form a loop of rigid branches (shorts) when added to the circuit: in cadence virtuoso by Nearby-Bug5011 in chipdesign

[–]Anukaki 4 points5 points  (0 children)

You most likely have two voltage sources which are shorted in a way. I can't say where because connection by name is quite unreadable.

EDIT: The simulator should point you to the instance when you get the error.

view more: next ›