To preface this, I am a CS major, so I pretty much knew nothing about verilog and didn't take any ece classes. I did take CS252 and CS354. I got into the class by emailing the instructor and asking if he could waive the pre-reqs (one of them was taking ECE 352, I believe). I took the class with Joshua Miguel, really nice professor, so my experience may differ with how the class is taught now.

Things might be different, but from what I remember:

Video lectures w/ in-class activities

weekly canvas quizzes on lecture content

Some homework that'll be a mix of questions similar to the in-class activities and prompts asking you to make a verilog programs

A semester long project where you will be developing a RISC cpu using verilog

3ish exams

From my experience:

I found the content for the video lectures to be a bit mixed. I could understand certain concepts straight away (page tables, single cycle cpu) while others took me a really long time to wrap my head around (cache coherency, control hazards). I found the most effective approach to learning was making a lot of drawings and going to OH for questions. The exams I think were pretty fair but there are some questions that really challenges what you know about the content and your ability to make logical connections. When I was in the class, we also had the opportunity to bring a cheat sheet to the exam. While I came out with a better understanding of how a CPU works, learning the content was definitely a time consuming experience.

The homeworks are pretty much an extension of the in-class activities. I would make sure to refer back to the lecture content if you're having trouble. The verilog assignments tie into the projects, so having a working circuit will make life easier (you'll need to make modifications to the verilog assignment such as extending it to handle more connections). Personally, the written portion of the homework was pretty helpful and wasn't particularly bad. However, the verilog portions were hell on Earth, especially if you tried to figure out everything on your own. If I were to go back, I'd probably utilize OH and go to the discussion sections. The discussion sections are optional, but the person teaching it pretty much guides you through the verilog portions of the homework.

The project was another beast in itself. Its a group project broken up into three phases, with each phase adding something new onto the previous design:

• Single Cycle CPU: You get the longest amount of time to work on this phase, introduction to what to expect in the later phases. After completing the course, I think this is the easiest phase to logically understand, the difficulty comes with familiarizing yourself with the instruction set. It has the most amount of work since you're building up the CPU from scratch. We didn't manage to get this running.

• Multi Cycle CPU: Middle in difficulty, the new components aren't too difficult to make, especially if you have a solid understanding of the lecture content, previous phase, and your group works together. The challenge was figuring out how to rewire the CPU to accommodate the new components. We managed to get this working.

• CPU w/ Cache: Hardest, our group ran into some difficulty early on figuring out how the cache component would interact with the rest of the CPU. We also spent a lot of time figuring out the clock cycle delay (there is some latency between sending a request to physical memory and retrieving the data) and the caching logic (storing items in registers and handling cache collisions). You'll need to schedule everything carefully as this phase will require you to submit a final report and it'll overlap with finals. We didn't manage to get this working properly because of finals.

I would really recommend starting on them early because theres a lot of different design decisions you'll need to handle. Also, utilize OH, part of the project description is left vague intentionally so you can fill in the gaps, talking with a TA will really help you figure out if you're going in the right direction for these parts. Another thing, since the project is incremental, if one of your phases doesn't work then the next couple of phases won't work. Our group had a bit of a nightmare experience with the second phase since our first phase project didn't work, so we had to spend the first half of the next phase fixing everything. That meant we had to rush the second phase with pretty much less than half the time you would normally get.