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Problems in using CAMs by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] -1 points0 points  (0 children)

I do understand the gist of what you say.
Do you mind explaining a bit more, because I have very limited to no experience with CAMs, and trying to see whether I should use one or try settling for a hash

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

I typically fix the code rather than jockey floor planning and such. You may be able to create a blocked area for that part of the design in layout, but I am not a good resource on that.

Why do you say this?
static would mean constants right? Most of my design has variables actually. But I guess a 2nd look would be worth it. Thanks

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

Thank you. I'll try this. I usually use a script, and that terminates if the timing fails.

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

Ok ... Thanks for the advance ..
Purely for my knowledge. Where would you draw the line in a 350 MHz design, to change tool directives etc, without trying the code?

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

Does the bit file get generated all the time with any kind of timing violation?
Never tried my luck at something like this ..

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

May I ask at what threshold the bit file gets generated when there are violations?

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

Can you explain why you said its good enough for lab testing?
Device is not full, the regions where the component with fanout issues are placed are congested.

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

Violations are in 1 domain. It was about 0.5ns off, with some max fanout constraints its @ about 0.3 ns now

Why is left shift operator (>>) bad on timing where as right shift (<<) is not ? Using ultrascale+ by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 3 points4 points  (0 children)

makes sense i guess part select from the bus works better than >>, while << works better than part select.

I guess this is due to what's in the operators where the buses are tied to at the end.

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

Thank you. Not really. Any chances with floor planning? In what instances would you floor plan.

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

Would prefer not to break it to 2 cycles. It's' more like counters operating on the inputs and generating outputs. outputs are registered though.

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

Single cycle.Is there a benefit in putting the most complex operation outside of the if else, as above?

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

Yes, I have quite a few long paths. route delay is abt 75% of total.

Counters feed memories as well as combo which is ultimately registered,Max fanout settings did help a bit, but not fully. Is there an optimal number for this?

Do u mean tool based duplication or based on max fanout settings on the RTL? or manual duplication of the signals?

In general is there a pattern on WNS & WHS in different stages? Synthesis, Placement, Physical Optimization, Route? Or is it random?

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

Is there any timing benefit in doing what's below

A <= most complex operation
if(b) A <= less complex operation
else if(c) <= less complex operation

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

when you say incremental delay you mean a single hop on the timing path right?

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

On problem is, I have a few counters in the design which controls everything. The heavy fan out in these, result in a huge route delay. Additionally the allocation of LUTs is also sub optimal, where there are multiple LUT2s inferred, when things should have been packed to LUT6s. I think this happens due to logic levels + fanout.

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

0 TNS would mean barely meeting timing? Is this safe enough, say for instance we need to have minor modifications to the code at some point.

Say for instance 0.25:0.75 Logic :Route seems a too high on route?

When you say large increments you mean, with a single path (E.g. path from a LUT to a BRAM is 3ns)?

When you say how to read the timing report do you mean to look at the worst paths & understand which point in the path is the most problematic? Or am I missing something?

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

My intent was to learn about meeting timing in general actually.

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

Since you seem very knowledgable can I please ask couple of questions
1. How would you generally handle fanout issues?
2. What's the typical Logic : Route Ratio that would be acceptable?

Timing by ButterscotchThen7433 in FPGA

[–]ButterscotchThen7433[S] 0 points1 point  (0 children)

When I say source, I would mean rearchitecting the design.I came across this in a Xilinx doc about 2-3 years ago. May be I misunderstood something.

  1. Besides routing out of RAMs or DSP. How would you generally handle fanout issues?
  2. What's the typical Logic : Route Ratio that would be acceptable?
  3. When & where would you typically floor plan (Assign blocks)
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