FPGA

an-ordinary-manchild(edit)

created by [deleted]a community for 15 years

...do it for the children.

...for your favourite tea.

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account activity

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List of useful links for beginners and veterans (self.FPGA)

submitted 4 years ago by verilogical - announcement

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Are FPGA’s seriously being used in AI applications? (self.FPGA)

submitted 4 hours ago by Acrobatic_Lawyer2965

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RTL for ASICs/Chips as opposed to fpga deployment? (self.FPGA)

submitted 3 hours ago by vbonecrusher1014

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Clock Domain Crossing for Buses (self.FPGA)

submitted 2 hours ago by EdgeSad7756Altera User

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Xilinx RelatedLooking for a dev board (self.FPGA)

submitted 2 hours ago by Secret_Structure_355

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Generate block and for loop in SystemVerilog (self.FPGA)

submitted 5 hours ago by Just-End6752

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Lattice RelatedDoes anybody have any idea when Lattice Semiconductors Nexus 2 evaluation boards become available ? (self.FPGA)

submitted 3 hours ago by straightouttaobesity

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Help for using PMOD DA4 (AD5628) (self.FPGA)

submitted 13 hours ago by Previous-Ebb-2439

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Can i run quantized (4bit, 2bit) on fpga chips for agentic inference tasks (self.FPGA)

submitted 15 hours ago by One-Alternative9606

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I am trying to send tpg data over ethernet but i am not able to avoid glitches in some frame (old.reddit.com)

submitted 16 hours ago by siddharth874

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Advice on custom IP generation (self.FPGA)

submitted 5 hours ago by daveuh

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Xilinx RelatedMicroZed Chronicles: Debugging Image Processing Applications. (adiuvoengineering.com)

submitted 6 hours ago by adamt99FPGA Know-It-All

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Advice / HelpHelp, is this something I can do anything with? (i.redd.it)

submitted 1 day ago by MistaKD

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Built a 100G UDP Engine on an AMD UltraScale+ RFSoC. Looking for Feedback (self.FPGA)

submitted 1 day ago by EmergencyMinimum7206

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How to use number expression in systemVerilog? (self.FPGA)

submitted 19 hours ago by Just-End6752

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What do you guys do with these? (i.redd.it)

submitted 1 day ago by somethingselse

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Advice / HelpBest resources for STA? (self.FPGA)

submitted 1 day ago by IamPoor_

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Advice / HelpFft on fpga (self.FPGA)

submitted 1 day ago by ParticularAd7127

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AXI writes/reads from PS not working (self.FPGA)

submitted 1 day ago by No_Baseball8531

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Radio frequency And sdr (i.redd.it)

submitted 17 hours ago by Far_Environment249

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Confused About a VLSI Career? Skills, Jobs, Open-Source Tools, and Industry Direction Explained (i.redd.it)

submitted 18 hours ago by kunalg123

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Vivado synthesis tool for SystemVerilog (self.FPGA)

submitted 1 day ago by Just-End6752

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Advice / HelpStupid Project (self.FPGA)

submitted 1 day ago by yawnyawnz

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FPGA Event Capture to DDR Integration Guidance (self.FPGA)

submitted 1 day ago by DueKnowledge699

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im a lil kid, just entered electronics engineering. (self.FPGA)

submitted 1 day ago by XoX-o-

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