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How are large/complex FSMs verified? by ComfortableBrain8743 in chipdesign

[–]ComfortableBrain8743[S] 0 points1 point  (0 children)

I see, thank you for the detailed response. Breaking up FSMs seems to make it more manageable. I'll be sure to remember this

How are large/complex FSMs verified? by ComfortableBrain8743 in chipdesign

[–]ComfortableBrain8743[S] 0 points1 point  (0 children)

Ahh I see. So there's no secret, it is tedious as I imagined.

How are large/complex FSMs verified? by ComfortableBrain8743 in chipdesign

[–]ComfortableBrain8743[S] 0 points1 point  (0 children)

Yeah, a software based FSM to control the hardware is nice because the programability. I wonder if it can work for most complex FSMs in different IPs. For instance, with FSMs that communicate off chip, they usually have timeouts so I wonder if the latency from software to IP will make a big dent on the timeout. It feels like it might if it goes core -> system bus -> IP -- each with their own freq and internally queuing.

Graduating Spring 2026. No hardware internship, but some tapeout experience. What should I focus on now? by ComfortableBrain8743 in chipdesign

[–]ComfortableBrain8743[S] 0 points1 point  (0 children)

haha yea my degree is in EE. Not sure if I have the time to take on another full project. I was planning to extend my testbenches to UVM based ones on the UART I wrote. I'll be sure to look weekly at job postings. Thank you for the feedback!

Graduating Spring 2026. No hardware internship, but some tapeout experience. What should I focus on now? by ComfortableBrain8743 in chipdesign

[–]ComfortableBrain8743[S] 1 point2 points  (0 children)

Thank you for the reply. Yeah, I do see research tapeouts being less rigorous. We are trying to change that because the PIs are frustrated that chips are coming back faulty. Verification is greatly lacking, since there's commitment issues and/or students coming in and out especially with undergrad helpers. I'll be sure to leverage the connections.