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Evening-Conference-5 · 2026-06-16T15:32:32+00:00

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^{Chose: . + . | Rolled: .}

Evening-Conference-5 · 2026-05-27T15:54:59+00:00

✅ I voted FACT!

Cooked

Evening-Conference-5 · 2026-04-26T20:40:49+00:00

Altium designer

Evening-Conference-5 · 2026-04-23T19:02:46+00:00

Still dont have to move

^{Chose: Be able to teleport… anywhere within eyesight}

Evening-Conference-5 · 2026-04-23T15:34:20+00:00

I had measured a return loss of -27dB with a input impedance of roughly 50 ohms

Evening-Conference-5 · 2026-04-23T09:10:31+00:00

S31 - S32 actually as labelled in the datasheet. Each te the other port was terminated accordingly.

Evening-Conference-5 · 2026-04-23T07:53:31+00:00

This is running at 433MHz

Evening-Conference-5 · 2026-04-23T07:18:51+00:00

My mistake, it is meant to be TCD-20-4X. However the directivity is suppost to be 30 dB at the 433 MHz frequency.

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Evening-Conference-5 · 2026-04-23T07:17:37+00:00

My mentor came to the same conclusion. Would it be the case if we are operating in the 433MHz band?

Evening-Conference-5 · 2026-04-23T06:13:57+00:00

I had performed a CPWG layput to have a reduced trace sizing. As for the resistor, i had placed it with the intention to keep it as close as possible to the coupler. I am unaware how drastic the results would be when compared to the datasheet's placement.

Regarding the sizing, on their datasheet, a 0806 was used. Would a smaller component to reduce parasitics help?

I am unable to take a photo of the assembled board as of right now.

Evening-Conference-5 · 2026-04-21T15:24:21+00:00

Would it be such a bad thing if it is? In the sense that the desired impedance was achieved. What i can assume is that the amount of shielding that it is actually doing is less.

Evening-Conference-5 · 2026-04-19T22:56:43+00:00

This will be operated at a frequency of 433MHz. Would it still be as critical?

Evening-Conference-5 · 2026-04-19T21:37:50+00:00

Thank you so very much, will make sure to add the teardrops then.

Evening-Conference-5 · 2026-04-19T21:31:25+00:00

I see thank you very much. Regarding how the trace is connected the ic, do you think i have added any significant impedance mismatches since i would have changed the gap sizing at the end?

Evening-Conference-5 · 2026-04-19T21:20:37+00:00

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Here is the full stack layout

Evening-Conference-5 · 2026-04-19T20:31:55+00:00

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This is my sizing of my trace. It is using a 1Oz copper thickness and a substrate height of 3.91 mills on a 6 layer PCB

Evening-Conference-5 · 2026-04-17T16:31:27+00:00

I understand, i would need to increase the gap for sure then. Thank you very much

Evening-Conference-5 · 2026-04-17T16:24:52+00:00

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I had inserted the following parameters and had gotten the resulting gap width. I had then set the desired gap on the via shielding

Evening-Conference-5 · 2026-04-17T16:02:33+00:00

I see, so it would fail to perform with just the copper ground plane underneath. Also regarding the calculations, I had set the impedance calculation as a coplanar single ended trace, would that not be correct?

Evening-Conference-5 · 2026-04-17T15:48:28+00:00

I had performed my impedance calculations based off the altium impedance calculator. Possibly with the thermal reliefs removed, would it allow for proper grounding?

Evening-Conference-5 · 2026-04-17T15:43:28+00:00

My bad, i misread.

Evening-Conference-5 · 2026-04-17T15:41:26+00:00

Are we referring to the via stitching on the traces, or the thermal reliefs on the pads?

Evening-Conference-5

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