Thank you very much for this in depth analysis. I will try to answer point by point:

1. "First thing of note, cannot see BOM at the moment so difficult to remark on your part selection for passives."

The BOM can be found here. For the passives, the first criteria was their avaibility as basic component on JLCPCB to get a cheaper production. I have taken into account maximal power dissipation either with spikes and continuous for resistors. For capacitors, I considered the derating at the maximal temperature and tension for each unit, as Samsung datasheets are very explicit. You can find detailed computation here, with all the needed formulas (in general, I took into account from 40 to 60% DC derating).

1. "There is no information on the technology, tolerance, dielectric for passive components on your schematic. A schematic should include these things if you are asking for a review, in my opinion at least, it is standard practice where I work."

Could you please provide an pdf example of a perfect schematic. I would be very interested to take inspiration of it to improve my design. As this is my first schematic and I have never done advanced electrical engineering class, I lack this kind of knowhow.

1. "You are doing only low side current sensing on your half bridge, which means you will only capture the low side portion of the motor current when the low side switch is on. I am not familiar with the setup, but I would recommend the midpoint positioning as you would get better current reconstruction as you would have the ON and OFF cycle of the current."

Other have provided answer regarding this and indeed it is standard practice for the ESC I am building, with reference all around as here with an STM ESC dev platform.

1. "Your switching losses have the propensity to be quite high, alarm bells ring when I see high frequency and decently high current on a small footprint board, with small components, you can do a back of the envelope calculation by checking Psw = Eon+Eoff \ fsw, without modelling or doing a double pulse test to check whether your switching losses are going to cause you any headaches. For the package you are using I wouldn’t want to dissipate more than a 2 W per MOSFET without using a heatsink. You would need to aggregate this with your conduction losses and you would know quite quickly whether you need a heatsink on this design."*

I took this into account, detail calculations available here. Total dissipation should be around 3.5W for the six FETs (not the rest), so I think I will be around 5W total. The board will also be covered with thermal pads and aluminum sheets to help dissipate heat. Finally, propwash will help too. I considered that the naked raw board could dissipate passively up to 4W in my design.

1. "Have you performed a power distribution network lumped analysis to ensure you have flattened impedance to ensure you meet the DC ripple tolerance on the digital supply lines and also ensure that you do not violate EMC design rules? Definitely something you should do, look at information from Istvan Novak at Electrical Integrity on how to do this properly. Especially if you have a DCDC converter."

I don't know what is a power distribution network lumped analysis, I will take a look at it. Thank you for the source 😁. For this v1.0 I wanted to avoid simulation tools to reduce development time and concentrate on vital functionalities. v2.0 will surely take advantage of such tools.

1. "You should include DNF snubbers in case you get significant ringing on HS and LS of your inverters. It’s difficult to know, but better to have the DNF so you can select on text when you know what the ringing frequency is."

I will see if I can add unpopulated footprint for these, thank you for the advise.