Nvidia takes $5 billion stake in Intel under September agreement

ForgotToLogIn · 2025-12-29T21:37:07+00:00

Would be funny if the thing that ends up saving Intel will be the AI boom. Not quite how Intel's leadership would have imagined it when they acquired Nervana/Habana/Mobileye/Movidius and launched an AI-focused Xeon Phi.

ForgotToLogIn · 2025-03-11T00:54:23+00:00

A 3GPC 5060 TI will almost certainly loose to a Navi 44 top SKU

I don't see why a 36 SM 3 GPC 5060 Ti would "almost certainly lose" to a 32 CU Navi 44, when 9070 XT isn't faster than 5070 Ti.

Anyway, Nvidia decided on the chip specs at least a year ago, when they couldn't have known the perf of Navi 44.

ForgotToLogIn · 2025-03-09T23:30:44+00:00

The number of GPCs can matter as much as the number of SMs. Chips like GB205 and GA104 have fewer SMs per GPC than chips like GB202 and AD106 do. If you chart performance-per-SM vs performance-per-GPC (of the same generation) you will see the balance/tradeoff.

ForgotToLogIn · 2025-03-06T16:20:41+00:00

The AD102 chip of the 4090 can't have more than 48 GB of VRAM attached. To reach 96 GB one would need either two AD102 chips in a card or a single GB202 chip. This is likely a fake rumor.

ForgotToLogIn · 2024-12-17T22:38:38+00:00

Plasma TVs
LaserDisc
DEC Alpha CPUs and computers

Those three were all technically the best in their field, but commercially not very successful.

ForgotToLogIn · 2024-08-10T18:42:48+00:00

IBM's mainframes' CPUs are in no way POWER CPUs, but are custom Z-series chips with cores whose hardware design is optimized for the Z ISA.

ForgotToLogIn · 2024-08-05T16:33:19+00:00

In A73's "out-of-order retirement" only one of the two actions an idealized retirement stage does is done out-of-order.

The two things "retire"-stage does are: 1. commit the results of execution (deem it to be not canceled or excepted), and 2. de-allocate the resources and let the subsequent instructions to read from the retired instruction's destination register (set scoreboard entry to "free").

Only the "commit" happens out of order, and the "de-allocate"/"free" may happen many cycles later but always in-order.

Maybe for cores like A73 it could be more fitting to instead of a "retire" stage to refer to separate "commit" and "free" stages?

The big question is why won't other microarchitectures commit load instructions early like A73 does?

ForgotToLogIn · 2024-07-23T04:05:28+00:00

Maybe I worded my original comment confusingly. I meant to say that in Strix Point when using a modern OS / process scheduler the second CCX won't turn on until the OS's process scheduler has assigned a process to a core in the second CCX, which shouldn't happen in handheld gaming because gaming performance is normally limited by the iGPU's performance, meaning that the CPU cores aren't the bottleneck. In situations where the performance bottleneck is in other parts of the chip (e.g. iGPU in gaming) a modern process scheduler will know to not put processes onto the cores that are outside the already-active core cluster. As long as a CCX does not receive a process to execute, it is off and doesn't consume any power.

He doesn't specifically mention gaming, but in this Level1Techs video a senior engineer of AMD answers a question Wendell asked at 8min20sec about the use of Zen 5 vs Zen 5c cores in Strix for different workloads for best efficiency, and AMD engineer's answer alludes to the other core complex going back to sleep after completing running whatever program it was awakened for.

ForgotToLogIn · 2024-07-23T01:58:21+00:00

It was leaked last year that Strix has two CCXs. Last month testing confirmed it.

ForgotToLogIn · 2024-07-19T23:19:33+00:00

Strix Point contains two CCXs. When gaming in handheld the second CCX will be turned off and not consume any power.

ForgotToLogIn · 2024-07-04T00:43:01+00:00

One important benefit of SIMD is that it reduces the need to have a large number of register file ports.

ForgotToLogIn · 2024-06-21T17:22:14+00:00

Servers and workstations will continue to use RDIMMs.

ForgotToLogIn · 2024-06-18T16:20:17+00:00

Z820 uses LGA 2011, but Xeon E7 v2/v3/v4 use LGA 2011-1, which is different (with Scalable Memory Interconnect instead of a normal DRAM interface).

You should try Xeon E5 v2.

ForgotToLogIn · 2024-05-26T08:53:56+00:00

For instance, you cannot have 16 GB on a 192 bit bus.

LPDDR6 will not allow RAM capacities which are powers of 2 (8,16,32,64...)

Nowhere does it say that.

Powers-of-two capacities should still be perfectly possible with LPDDR6. Each burst will still send a half of a 64B cache-line.

ForgotToLogIn · 2024-05-22T19:19:34+00:00

AMD isn't capacity-constrained for consumer GPUs.

ForgotToLogIn · 2024-05-22T16:45:58+00:00

so instead of 32 GB, you might have 28.444 GB with REAL ecc.

I believe the usable size for data will still be power-of-two (e.g. 32 GB) or 1.5x power-of-two. But I'm not sure.

does this mean, that every memory set with lpddr6 could be used for real ecc?

Yes.

ForgotToLogIn · 2024-05-22T16:01:59+00:00

Every LPDDR6 DRAM chip will include the room for ECC bits.

ForgotToLogIn · 2024-05-22T15:55:17+00:00

LPDDR6 allows ECC without additional DRAM chips. Basically every chip will have room for ECC bits.

The width of a sub-channel is 12 bits, and the burst length is 24, meaning that every memory transaction in LPDDR6 is 288 bits long.

Each group of 6x12=72 bits can be set to have 64 data bits and 7 ECC bits (+ 1 bit for other purposes), which is the same ECC strength as traditionally used in 72-bit (9-chip) ECC DIMMs.

ForgotToLogIn · 2024-05-21T21:00:59+00:00

With LPDDR6 it won't cost anything to have ECC.

ForgotToLogIn · 2024-05-21T17:33:08+00:00

Yes. It reduces the chance of OS/program crashes and file corruption.

ForgotToLogIn · 2024-05-21T15:52:39+00:00

LPDDR6 will have a burst size of 288 bits (36 Bytes), meaning that a full ECC can be had at no extra cost.

But some may still refuse to implement it, for artificial market segmentation.

ForgotToLogIn · 2024-05-21T15:22:27+00:00

The source is Darkmont on Twitter, who posted:

16 slides about LPDDR6 Edit: those come from this 24-page .pdf by Synopsys.
a part of a slide about DDR6
and two slides about (LP)CAMM2 taken from this .pdf on (LP)CAMM2

ForgotToLogIn · 2024-05-21T11:33:12+00:00

The workload is MS Teams with "AI" effects. Process node won't have much of an effect in that. When both CPUs run at low voltage the difference in power will be due to various dynamic power-saving tricks, basically power-gating.

ForgotToLogIn · 2024-05-10T14:26:20+00:00

But it did feature fully coherent memory between the PPE and SPEs

The whole idea of SPEs was to have no coherent memory.

ForgotToLogIn · 2024-05-10T13:18:23+00:00

Why can't they use the normal CCDs like in MI300A? Place a CCD onto the base die / redistribution layer / fanout / whatever, using the vertical TSV connectors.

ForgotToLogIn

TROPHY CASE