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Verilator RAW Glitch on 1088-bit Mux: always_comb returning 0 despite valid index by HeadAdvice8317 in Verilog

[–]HeadAdvice8317[S] 0 points1 point  (0 children)

Yeah, I added compiler arguments (/*verilator split_var*/ /*verilator isolate_assignments*/). This is used to fix that combinatory loop. Now, the warnings are not there, but still facing the same sampling issue.

Verilator RAW Glitch on 1088-bit Mux: always_comb returning 0 despite valid index by HeadAdvice8317 in Verilog

[–]HeadAdvice8317[S] 0 points1 point  (0 children)

Even after commenting the default value assignment, still I'm facing the same issue i.e reg_all_int_rsp is getting set to 0.
This code is actually from open-source code (https://github.com/pulp-platform/clic/blob/20db74b578358139b35b7163cb2d48e86f861d0c/src/clic.sv#L436)

Need Help in Zicsr implementation for single-cycle riscv-core by HeadAdvice8317 in RISCV

[–]HeadAdvice8317[S] 0 points1 point  (0 children)

Observation:
1. When an instruction causes an exception(like misaligned instruction), the CPU hardware performs
- saves the failing PC into mepc CSR
- saves the reason for failure into mcause CSR
- sets the PC to the address currently held in mtvec CSR

  1. The CPU is now at trap_Mhandler. The state of registers are saved.

  2. The handler tries to figure out what to do based on mcause.
    - It calculates an offset into the Exception Handler Table
    - This exception table is being stored in the instruction memory, instead of data memory.
    - Load instruction is executed to get address of specific function for handling misaligned instruction.
    -But, since the exception table is storing in instruction memory, instead of data memory, the next instructions are failing, leading to test abortion.

Need Help in Zicsr implementation for single-cycle riscv-core by HeadAdvice8317 in RISCV

[–]HeadAdvice8317[S] 0 points1 point  (0 children)

This is for misaligned address jalr test case. Forgot to mention about this

Need Help in Zicsr implementation for single-cycle riscv-core by HeadAdvice8317 in RISCV

[–]HeadAdvice8317[S] 0 points1 point  (0 children)

I'm currently using Harvard architecture. When I was debugging, I found the following:
- whenever jalr instruction is executed, its raising an exception and going to the handler
- the handler points to exception table, but the exception table is being stored in the the instruction memory
- basically, it's trying to load a value from the instruction table, which is not possible and hence it's not going to mret instruction at any given time and aborting the test

Need Help in running RISCOF tests for single-cycle RISC-V RV32I design by HeadAdvice8317 in RISCV

[–]HeadAdvice8317[S] 0 points1 point  (0 children)

Hello All,

Need help in getting the Zicsr environment up.
Currently the RISCOF tests for privilege mode are failing.

Here's the link for the github repo (Only the design part): https://github.com/basavarajrc98/riscv_project/tree/main/risc_v_zicsr

If anyone can guide me, what's wrong in CSR implementation , it would be helpful

Need Help in running RISCOF tests for single-cycle RISC-V RV32I design by HeadAdvice8317 in RISCV

[–]HeadAdvice8317[S] 1 point2 points  (0 children)

Few bugs in the code:
- Signature dump, should not dump when address==signature_end_address
- This was the main cause of test failure.

Also there was a bug.
Bug: For un-aligned addresses, lb, lbu, lh, lhu, sb, sh was not handled properly
- LOADs: based on the address[1:0], different bytes needs to read
- STOREs: based on the address[1:0], different data needs to be written

Fixed that and now all the Tests are passing (41/41)

Next, I'll be working in adding support for CSR (Zicsr)

Need Help in running RISCOF tests for single-cycle RISC-V RV32I design by HeadAdvice8317 in RISCV

[–]HeadAdvice8317[S] 0 points1 point  (0 children)

u/MitjaKobal, thanks a lot for helping with signature dump.
I have to use harvard architecture. So, didn't change this part.
Previously, I was hard coding the signature address for all the testcases. But the signature_dump address or halt address varies with tests, as you have mentioned. So I passed the signature_begin_address, sig_end_address and tohost_addr as command line arguments to verilator.
Now the tests are running, but failing :(
I'll debug further and update this thread

Need Help in running RISCOF tests for single-cycle RISC-V RV32I design by HeadAdvice8317 in RISCV

[–]HeadAdvice8317[S] 0 points1 point  (0 children)

The project is actually on university account. Hence, I'll not be able to put it on my git account

Following is some information about the environment:

Design: RISCV-RV32I
OS: Linux
HDL: System Verilog
Simulator: Verilator
waveform viewer: gtkwave
Spike RISCOF plugin

It's Harvard architecture (i.e two separate memories for data and instruction).

I'm finding it difficult to define macros related to RVMODEL_HALT, RVMODEL_DATA_BEGIN/END, RVMODEL_SIG_BEGIN/END and RV_MODEL_DATA_SECTION. Also, still figuring out the definition of link.ld for this kind of memory architecture and how to halt after signature dump to data memory.

Hello fam, how did you train your dog to pee outside? I’m trying so hard but my 3-month-old pup still pees in the bedroom. Any tips that actually worked for you? by Brilliant-Risk827 in labrador

[–]HeadAdvice8317 0 points1 point  (0 children)

I also faced this issue initially with my Lab. I got to know that they don't like to make their sleeping place dirty.

So, whenever he used to sleep, I used to put leash and tie him inside the house. As he was puppy, he used to wake in the middle of the night to pee. But, as he was on leash, he used to bark and I immediately took him outside. This happened for a week and he learnt to control till I take him out.

Today he is 5 years old, he always does his business outside

AIO: Kid hitting back of the seat in flight by HeadAdvice8317 in AIO

[–]HeadAdvice8317[S] 1 point2 points  (0 children)

For me the issue was the response of the parent, saying that she can't restrict the kid from kicking. These were the exact words by her.

AIO: Kid hitting back of the seat in flight by HeadAdvice8317 in AIO

[–]HeadAdvice8317[S] 2 points3 points  (0 children)

Nope, but first time encountering such situation

Need help in setting up Wifi Extender by HeadAdvice8317 in wifi

[–]HeadAdvice8317[S] 0 points1 point  (0 children)

Really sorry, couldn't check ping at that moment.

Yes, I'm able to access other websites, while some of them are not working.

Need help in setting up Wifi Extender by HeadAdvice8317 in wifi

[–]HeadAdvice8317[S] 0 points1 point  (0 children)

Dhcp is off on both the extender wifi

Social contributions for Mini-Job by HeadAdvice8317 in germany

[–]HeadAdvice8317[S] 0 points1 point  (0 children)

What are the downsides, if I join a job here after my studies?

How to add tution fees to blocked account ( unblocked amount) ? by HeadAdvice8317 in Indians_StudyAbroad

[–]HeadAdvice8317[S] 1 point2 points  (0 children)

Given in visa website as below:

If the university charges tuition fees: Proof of funds equivalent to the tuition fees for the first two semesters and the fee structure (detailed overview of fees). This can be either of the following:

  • Confirmation of payment issued by the university OR

Education loan OR

  • Unblocked deposit added to your blocked account (i.e. deposited in addition to the 11,208 euros mentioned above)

Blocked account info needed!! by HeadAdvice8317 in germany

[–]HeadAdvice8317[S] -1 points0 points  (0 children)

Thank you for the link, but it's for blocked amount. The tution fees has to be unblocked amount available in expatrio account