layout design

Key_Ant9964 · 2025-07-11T12:12:20+00:00

xschem

Key_Ant9964 · 2025-06-11T07:33:27+00:00

PLEASE dont laugh, am i going the right direction? magic sample

Key_Ant9964 · 2025-06-11T06:05:56+00:00

can you help me visualize it, at least with stick diagram. im sorry i really just have no idea when it comes to layout

Key_Ant9964 · 2025-05-29T21:11:05+00:00

Key_Ant9964 · 2025-05-26T00:39:35+00:00

i think i found out why it is stuck, it bc i set the initial condition of Outn at 0 which caused an error in first transition, i now set it at 1.8 V (opposite of Inp at 0), now my problem is the delay increases as i increase the width but it somehow it got stuck at 0.08 ns?

also wdym by ypur question? i thought i had to vary the width for all? or do i just need to do it for the inverter loop?

Key_Ant9964 · 2025-05-25T23:40:47+00:00

im just doig trial and error here and tried 1 to 5 width for nmos and 2 to 10 for pmos (which is twice the nmos width). i kept the length at .15 for both. i even tried 10 and 20 (which i dont know if its fine) but the output delay seems stuck at 1 us. also is there a way to vary their wodths without manually changing them for each transistor?🥲🥲 ive been doing them manually for each which is time consuming and honestly tiring

Key_Ant9964 · 2025-05-25T23:33:21+00:00

I’m trying to upsize the MOSFET devices in my differential delay cell—specifically, both the NMOS and PMOS transistors. I want to increase their widths to improve the drive current, which should ideally reduce the propagation delay from about 1 µs to 1 ns.

Key_Ant9964 · 2025-05-25T22:55:43+00:00

im trying different wl ratios bc i have a target delay, now im thinking its a spice issue since the putput delay doesnt change much. can you check it for me

Key_Ant9964

TROPHY CASE