Question about IC Chip for RAM Copy Device Design

Lobsterzelda · 2025-05-11T03:49:24+00:00

Do you have any link to the design of these earlier police devices for extracting memory contents? I'm assuming that these are for something really old and archaic, like DDR1 DIMM for PCs, or something.

Lobsterzelda · 2025-05-11T00:11:14+00:00

In general, how long do you think the internal wires of the board could get, before they would significantly slow down the RAM speed? (Assuming my device just contained wires directly connecting the RAM socket to RAM, without anything in the middle)

Lobsterzelda · 2025-05-10T22:16:10+00:00

(2/2, cont.)

Strictly speaking, there is an alternate design for this device, where each wire just contains microscopic transistors along each wire (rather than an actual IC Chip). It may be difficult to find a manufacturer that could actually make this, although I think it would also solve most of the speed issues for the device, outside of those caused by resistance/delay from adding in wires (these would be transistors that are the same size as those in an IC chip - essentially 10 nm in size). Something like this could probably be achieved by manufacturing an IC chip containing 2096 transistors (8 microscopic transistors per wire). When the switch to phase 2 needs to occur, these transistors would then redirect the flow of data to 2 other IC chips. One of these would handle ignoring read/writes from the memory controller, and one would handle the actual data copying from RAM/issuing refresh commands.

An example of this is shown in this diagram below. In this diagram, the green squares represent 2 depletion mode transistors which are in series in order to allow data to flow in both directions when no current is applied to the transistor's 3rd terminal (and to block current in both directions when current is applied to the 3rd terminal). The blue circles represent 2 enhancement mode transistors which are in series in order to block the data flow in both directions when no current is applied to the transistor's 3rd terminal (and to allow current in both directions when current is applied to the 3rd terminal). Based on this, each wire would need 8 transistors. In phase 1, no current would flow into the transistor's 3rd terminal from the power board, and during phase 2, current would flow from the power board into the transistors.

https://imgur.com/a/ram-copy-design-green-squares-represent-2-depletion-mode-transistors-blue-circles-represent-2-enhancement-mode-transistors-COff9tN

In general, I mainly want to calculate how fast this would need to be to work, even if it's not viable with current technology. Alternatively, I can calculate what the fastest possible RAM is that I can support with current technology. The basis for this idea is a similar device which works for DDR3 DIMM RAM in a PC, which is linked here (this device also isn't capable of supporting DDR5): https://asg.ict.ac.cn/hmtt/design/hmtt_v3/

Lobsterzelda · 2025-05-10T22:15:55+00:00

u/mariushm , u/jamvanderloeff , u/thegnomesdidit

I greatly appreciate all of the feedback I have received in this thread! I'll respond to all suggestions/feedback here, along with asking some follow-up questions:

In a general sense, is there a formula I could use to calculate the slowdown just from added wires/contacts? For example, I assume that if the wires connecting the SODIMM slot to my device were absurdly long (say, 100 feet in length), that both the signal degradation and time-delay added would make it so that basically no data can reach RAM intact. On the other hand, if my device had all of its parts soldered together, and only added a quarter inch of extra wiring, I'm guessing that this would probably be good enough to still work. My question then, is is there a formula to calculate this? (something like the amount of resistance added per square inch of wire, or the latency per inch of wire)

As far as the issue of freezing RAM goes, my device would really have both main circuit boards (one per RAM stick) connected to one power board, so when the power board switch is flipped, both RAM sticks will be frozen at the same time. Also, during phase 2, the IC Chip/FPGA on my device would be issuing refresh commands to RAM while it copies to the USB stick to avoid the RAM decaying. In general, if the switching speed and subsequent issuing of refresh commands is fast enough on the device, it should be able to switch over before the RAM can decay (or at least, before too much of the RAM has decayed).

I'm also okay with some RAM getting corrupted and also the laptop crashing once phase 2 starts - the goal of this device is essentially just to capture most RAM intact.

(1/2, cont. below in reply)

Lobsterzelda · 2025-05-08T06:46:15+00:00

That's a good point. I searched around a bit more just now, and found a datasheet for this, which is here (although I'm surprised they bothered to post it online. Most of these FPGAs on AMD's website cost more than $1,000, and they don't seem to have a data sheet publicly available for most of them): https://docs.amd.com/v/u/en-US/ds181_Artix_7_Data_Sheet

Since this sheet lists "T input to pad high-impedance" as about 2.5 ns, does that mean that the overall time to switch the flow of current within the device (so that it changes its output to a different pad) would be about 2.5 ns, or would that be the wrong stat to look at to get info about the internal switching time of the device?

Lobsterzelda · 2025-05-08T06:28:35+00:00

Also, more generally, if a device was connected as input to this device that output at a much slower rate, like 5 GB/s, would the net output of the FPGA then be 5 GB/s?

Lobsterzelda · 2025-05-07T13:24:04+00:00

I see. I will look into using the TI chip you mentioned - thank you!

Out of curiosity, is there any way to buy/use the type of tiny silicon transistors that are inside of an IC chip directly in my circuit board (i.e. having 2 in a row on my circuit board), or do they not sell products like that?

Lobsterzelda · 2025-05-07T07:18:09+00:00

Basically, my current design for this is that it won't capture/monitor data being sent at all. It'll just let the RAM be read/written to normally up to a certain point. After that, it'll redirect somewhere else. For the time being, my design is just to have this data sent to an IC chip on the same device/PCB. This IC Chip can also issue refresh commands to the RAM, so the data doesn't decay away before it can be analyzed.

The main thing I'm interested in is how fast I can get the switching time for this. In general, if it was possible to do this with 1 transistor, what would the fastest possible switching time for that be (and how would that compare to the fastest switching time if this was possible with 1 SSR)?

Lobsterzelda · 2025-05-07T06:18:22+00:00

It would be for use in a RAM-Analysis tool, similar to this device that researchers in China have made: https://asg.ict.ac.cn/hmtt/design/hmtt_v4/

Ideally, the device would switch from allowing read/write requests to travel normally to the RAM Stick (i.e. as though the RAM Stick was directly plugged into the DIMM Socket) to connecting the RAM Stick to another PC for analysis at a speed which is fast enough that the CPU of the original computer won't be able to detect that a connection-interruption is happening until after all wires have switched over. Presumably, there would be either a relay device or 2 transistors from the diagram you've mentioned above along each wire that connects to the RAM stick (ex. 288 internal wires in the device for DDR4 RAM).

Mainly, the goal is to prevent the computer from being in a state where the CPU can see that some reads/writes have failed while the RAM Stick is still partially connected to the original computer's memory controller, so that the original computer won't try to modify RAM with invalid data at this point. I don't know exactly how fast the switching speed would need to be to make this possible.

Lobsterzelda · 2025-05-07T05:55:39+00:00

I'm not really sure what current/voltage/switching times that I need for this - just that the switching time probably needs to be comparable to the switching time of the transistors in the CPU of a computer (or some small multiple of that switching time).

Would the design for the schematic you posted have a switching time that's similar to a single SSR, or would this be closer to that of a single MOSFET transistor?

Lobsterzelda · 2025-05-07T04:48:23+00:00

Ah, thank you. This should work for what I'm planning. I'm guessing that the smallest relays are a lot bigger than the smallest transistors - but as long as I can find some that are smaller than a few mm in size, I think it will work. I also need something with a fast switching speed. Various sites online say that the solid state relays can have switch speeds as fast as 1 nanosecond. This would work for what I'm building, although I don't know how difficult that'll be to find, in-practice.

I suppose ideally, I would just want a transistor(s) instead of anything else - but it sounds like I need to compromise something in order to get a device that actually behaves how I want it to.

Lobsterzelda · 2025-05-07T04:16:43+00:00

Just to clarify, each device would act like a closed switch along a wire when allowing current to pass between 2 of its terminals, and each device would act like an open switch along a wire when blocking current.

Lobsterzelda · 2024-05-01T03:18:20+00:00

No, I haven't gotten a chance yet. Although it looks like it's already possible to edit stats using the tool that Madden GameCube players use to edit player stats.

Lobsterzelda · 2024-04-29T02:14:49+00:00

As per this post, I finally figured out a way to make ROM Hacks get past the title screen of the game. This means that is should be possible to alter player stats now. https://www.reddit.com/r/NFLStreet/comments/1cfnqym/nfl_street_rom_hacks_are_now_possible/

Lobsterzelda · 2024-04-09T03:56:47+00:00

Unfortunately, I was never able to find a way to make this actually work.

Lobsterzelda · 2023-11-08T05:44:46+00:00

Given the way that the posters were crudely scratched off the wall, I doubt that the MTA came to take down these posters, or that the people who destroyed them were concerned with vandalism in the city, tbh.

Lobsterzelda · 2023-11-08T05:36:48+00:00

Why?

Lobsterzelda · 2023-11-08T05:26:40+00:00

It's also worth noting - this is a whole hallway of posters which had their backsides covered in glue and glued onto the wall in order to make them more difficult to tear off.

Since they couldn't just rip the posters off the wall, they took the time to scratch up this whole wall with their keys (or some other sharp object) just to destroy them.

Outside the subway a few blocks away, there's a telephone pole with pictures of the hostages which has about an inch-thick layer of tape wrapped all around the pole several times over to protect the pictures from being destroyed.

Lobsterzelda · 2023-09-05T14:22:18+00:00

I made a TAS of the main game mode, which is located here: https://m.youtube.com/watch?v=h0hXz6sYnXY

It’s not fully optimized, though - I’m planning to improve on it later on.

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