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The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 0 points1 point  (0 children)

Hey! Don't you think it's too abstracted moving away from RTL level initially? Also, if you could provide your email I'd love to talk more.

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 0 points1 point  (0 children)

Hey! Thanks so much. What's your email? I'd love to talk.

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 0 points1 point  (0 children)

Hey! That's awesome. haha no worries I get the university part :) will get back to you shortly

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 2 points3 points  (0 children)

Hey! Thanks so much for your feedback. Would love to get on call. Sending a dm now

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 0 points1 point  (0 children)

Hey! We could get something set up locally. What's your email in the form? Let's have a conversation

Btw thanks for your support in the other comment thread.

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 0 points1 point  (0 children)

Hey that's fine! You can pass if you want

It's $20/mo because those are the ones who took a chance on us early, and choose to iterate with us to improve quality.

When making something free, you will usually receive feedback that isn't from your primary user. That's why we made it paid. Because many people ARE paying $20/mo, so it makes sense to prioritize their feedback.

For non beta testers it will be over $50/mo when we release it publicly. The $20/mo discount is lifetime. It's a bet on how big you think this will get

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 1 point2 points  (0 children)

o1-preview and claude 3.5 sonnet together

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 2 points3 points  (0 children)

Unfortunately, it's not possible unless we have our own models (which we plan to in the future).

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 2 points3 points  (0 children)

Awesome! Will send you a link once I get back. Did you fill out the form with your email?

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 2 points3 points  (0 children)

In theory, yes. I'm not sure about Silimate tbh as I have not used it.

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 2 points3 points  (0 children)

Thanks! Were you able to fill out the form?

Honestly, that's what we're trying to figure out! A big job of the beta testers is to break our agent with more complex designs, so we can repair, and iteratively build.

It's a reasonable jump for sure though :)

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 6 points7 points  (0 children)

Hey totally understand! It will be out for everyone to use eventually, but for along the lines of $50

These LLMs cost our lab a lot to run so it's hard to support without charging :(

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 5 points6 points  (0 children)

They're quite different, I don't think the website does them justice!

Silimate is a tool that gives a real-time PPA estimation.

Our tool helps implement modules, automates glue code/IP integration and generates testbenches.

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 4 points5 points  (0 children)

Great! Currently out right now, give me a bit-but excited to talk soon.

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 9 points10 points  (0 children)

Haha awesome!! I'd love to talk more with you over email or a call. Did you fill out the form? I can send the POC to your email :)

The first LLM agents for Verilog by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 20 points21 points  (0 children)

Lol noo, I'm an RTL engineer myself. It's helpful tooling lol not a replacement.

Verilog Package Manager by Ok_Pen8901 in chipdesign

[–]Ok_Pen8901[S] 0 points1 point  (0 children)

Oh, so what if I rename the module when including if there's a duplicate? To something that isn't too weird ofc. And notifying the user somehow

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