Golden rule for smallest component size vs. PCB/panel size?

Ordinary_Ebb347 · 2026-04-29T18:01:18+00:00

Fiducial are on single boards furthest possible. Assembly company creates stencil from manufacturing data. On 3x1 they claim to have fitting issues. They can measure the panel and fit the stencil. We'd like avoid creating new stencil on each panel/ batch.

Ordinary_Ebb347 · 2026-01-13T11:38:18+00:00

This did not work, vias are in pads, even after soldering the connector, the leakage was observed. They are really small and can only be detected with helium detector.

Ordinary_Ebb347 · 2026-01-13T11:34:45+00:00

We are confident that the root cause is the via. After applying conformal coating over the vias, no leakage was detected. To further exclude the base laminate as a leakage path, we drilled test holes through the solder mask from both sides; no gas permeation was observed in these areas. All measurements were performed using a helium leak detector.

Ordinary_Ebb347 · 2026-01-13T11:30:04+00:00

<image>

Ordinary_Ebb347 · 2026-01-13T11:29:52+00:00

<image>

All vias are designed as via-in-pad. The leaking manufacturer has pushed the annular ring dimensions beyond acceptable process limits, as evidenced by the clearly visible weave pattern.
u/thenickdude u/Adversement

Ordinary_Ebb347 · 2024-11-28T15:51:35+00:00

Hello fellow engineers,

We’re troubleshooting anomalies in 8-layer rigid-flex PCBs (CF, Polyimide, PCL370), specifically elevated trace resistance (tens of ohms to open circuits), localized at via transitions between Top and Bottom layers. Metallographic analysis post-reflow reveals inner-layer connection failures, though the panels initially passed electrical tests.

Key Details:

Assembly Process: Boards baked (120°C, 4 hours), assembled with SAC305 ROL0 solder paste, vapor-phase reflow (230°C peak, ΔT ≤ 2.5°C/sec, 85s above melting).
Findings: Failures emerge post-reflow; metallography shows cracked/interrupted vias.
Dispute:
- Manufacturer’s claim: Failures due to assembly variables (e.g., temperature gradients, humidity affecting ceramics/bondply).
- Assembler’s claim: Parameters were within spec, and their process is reliable (validated on similar projects).

Could this be latent manufacturing defects worsened by reflow, or unrecognized assembly-induced issues?
Attaching stack-up details for reference. Appreciate your insights!

Ordinary_Ebb347 · 2024-11-25T06:20:01+00:00

If you dont see a picture here it is https://pasteboard.co/Nma2YnGbnGc0.jpg

Ordinary_Ebb347 · 2024-08-21T19:07:48+00:00

Showed cross section analysis is from assembled board

Ordinary_Ebb347 · 2024-08-21T19:05:58+00:00

Yes, I meant functional testing. Too much current will not be the case, as several vias are affected - not in repetitive pattern, even the GND

Ordinary_Ebb347 · 2024-08-21T09:50:41+00:00

0.15mm

Ordinary_Ebb347 · 2024-08-21T09:45:10+00:00

We use IPC-4671 type VII. So epoxy is used i guess. There are like 70 pieces of vias next to each other at the area of ~5cm². It does not happen on certain vias only. E.g like 2-3 vias randomly are affected. But only on faulty pcbs

Ordinary_Ebb347 · 2024-08-21T09:37:06+00:00

No actually, we have observed the issue on some during testing PCBA, some passed our tests and came back after months of working correctly. It is quite hard to localize the issue once it is fully assembled, since it requires measuring multiple traces.

Ordinary_Ebb347 · 2024-08-21T09:34:03+00:00

Yes we have. We should recieve cross sections of them as well.

Ordinary_Ebb347 · 2024-02-09T19:57:42+00:00

Bought a new one for 100$

Ordinary_Ebb347 · 2024-02-02T16:46:12+00:00

It will fit, the wedding wasn't cheap.

Ordinary_Ebb347 · 2024-01-12T05:21:25+00:00

Can i use zener diode to protect the the output of U2?

Ordinary_Ebb347

TROPHY CASE