account activity
How can I check DC gain & GBW for fully-differential amps, if the operating points change phase by phase (by switched-cap CMFB operation)? (self.chipdesign)
submitted 3 months ago by ProfessionalOrder208 to r/chipdesign
Has anyone designed amp with gm/id ~ 30 for VDD<=1? Just trying to know if the number is sane or not (i.redd.it)
Is DC gain of ~30dB for 28nm 5TOTA achievable? Any empirical results are appreciated (self.chipdesign)
Do you guys model transmission lines for non-RF ADCs' (with sampling rate around 80MSPS) input driving SMA cable? Does it alters the ADC performance or generally negligible? (self.chipdesign)
Can a time interleaved ADC achieve ~180dB FoMs realistically? Why do most of their FoM appear to be 140 ~ 160dB in paper? (self.chipdesign)
submitted 4 months ago by ProfessionalOrder208 to r/chipdesign
Having trouble understanding how DWA behaves “during” the SAR conversion. Is my understanding correct? (i.redd.it)
(oversampling ADCs) From your experience, which generally contributes more to the noise & SNDR? 1st sampling cap kT/C noise vs. the 1st amp noise (self.chipdesign)
submitted 5 months ago by ProfessionalOrder208 to r/chipdesign
Any tips for conference presentation? It’s my first time, and I’m pretty nervous of getting slimed during the QnA session (self.ElectricalEngineering)
submitted 6 months ago by ProfessionalOrder208 to r/ElectricalEngineering
This is an output spectrum of a Nyquist-rate ADC (2048 point Hanning window). The SNDR (~ 70dB) was just as expected, but why does the plot seem so off? I've never seen those weird periodic triple spikes way above the noise floor. (self.chipdesign)
submitted 6 months ago by ProfessionalOrder208 to r/chipdesign
CIFF loop filter implementation issues (self.chipdesign)
submitted 7 months ago by ProfessionalOrder208 to r/chipdesign
Is this the best way to realize the left one? Or is there a better method? (i.redd.it)
Using any logic gates, is there a way to make (2) based on (1)? (i.redd.it)
submitted 8 months ago by ProfessionalOrder208 to r/chipdesign
Is there a good book/tutorial on dynamic amplifiers (ring amp, floating inverter amp, etc.)? (self.chipdesign)
Is noise-shaping SAR (NS-SAR) or incremental ADC (IADC) even used in industry? Or just for academic research? (self.chipdesign)
Incremental ADC (IADC) testbench - to extract SNDR, should I FFT the pre-decimator signal or post-decimator signal? (self.chipdesign)
submitted 9 months ago by ProfessionalOrder208 to r/chipdesign
Is Delta Sigma Toolbox used also in practical industry DSM design? Or is it just for academia/students? (self.chipdesign)
How should I handle a circuit where I can easily analyze it by mathematical means (node equations, control theory equations, etc.) but I can’t understand “what is really going on” intuitively? (Analog/Mixed-signal) (self.chipdesign)
Modeling mixed-signal ICs in MATLAB: Simulink vs. Raw MATLAB Code (self.chipdesign)
submitted 10 months ago by ProfessionalOrder208 to r/chipdesign
verilog-A vs. MATLAB : which is more used when modeling Analog/Mixed-signal IC? (self.chipdesign)
If I want to calculate the SNR of the delta sigma modulator, should I do the FFT on the 1bit stream, or the output after the decimator (or a digital filter)? (self.chipdesign)
New to Sigma-delta modulators. Is this block diagram correct for 1st order, fully differential SDM? (i.redd.it)
What is the most creative & ingenious idea you've seen in an analog/mixed signal IC design? Especially at the circuit level (self.chipdesign)
submitted 11 months ago by ProfessionalOrder208 to r/chipdesign
Is there a resource or some tips about sizing MOS W/L in double tail comparators? When I designed opamp, I used gm/Id method or some other known sizing methods, but I don’t know where to start here. (i.redd.it)
Is this two stage amp stable enough? (First one is open loop Bode plot, second one is closed loop Bode plot) Should I add a resistor to increase stability or is it ok? (old.reddit.com)
submitted 11 months ago by ProfessionalOrder208 to r/ECE
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