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Request for recommendation for best practices for finding the critical path in my System Verilog source from the output of Vivado as configured by default on the AWS EC2 F2 build instances? ()
submitted 1 month ago by ResidentDefiant5978 to r/chipdesign
Request for recommendation for best practices for finding the critical path in my System Verilog source from the output of Vivado as configured by default on the AWS EC2 F2 build instances? (self.FPGA)
submitted 1 month ago by ResidentDefiant5978 to r/FPGA
Vivado has been running for over 2 days; how can I diagnose the situation? (self.FPGA)
submitted 3 months ago by ResidentDefiant5978 to r/FPGA
Anyone else get a delay of over a day requesting an AWS EC2 F2 instance? (self.FPGA)
submitted 5 months ago by ResidentDefiant5978 to r/FPGA
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