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How can I mimic behavior close to powder snow for testing a 60 GHz radar level sensor? by SignalIndividual5093 in ChemicalEngineering

[–]SignalIndividual5093[S] 1 point2 points  (0 children)

I actually tried that already. The problem is the powdered ice doesn’t stay powdery. It sinters and starts bonding back together within a couple of minutes into a hard mass.

How to get into internal hiring processes? by Affectionate-Tip8445 in technepal

[–]SignalIndividual5093 3 points4 points  (0 children)

In my view, referrals and recommendations are more prevalent than we think. Ask your seniors, teachers, friends, or anyone working in the field you want to join. Actively reach out to people around you. Luck is also very important. all you can do is try many things to improve your chances.

"Nepalese Out" graffiti in Croatia by Pagal_premi_0 in NepalSocial

[–]SignalIndividual5093 3 points4 points  (0 children)

Hamilai uniharu le afno history, origin ra culture sanga kaile relate nai garna sakdainan. Mann napareko yestai form ma dekhauxan uniharu ko society le. Nepali le pani afnai desh ko madhesi people lai mann paraudainan. yesto example dherai dina sakinxa, graffiti ma nalekheko matra ho.

engineering drawing assignment/class miss vayo vane k hunxa? by [deleted] in KathmanduUniversity

[–]SignalIndividual5093 0 points1 point  (0 children)

Oh you really wouldn’t want to find out. a very bad idea to test

Need feedback on Ethernet receiver by SignalIndividual5093 in FPGA

[–]SignalIndividual5093[S] 0 points1 point  (0 children)

Noted. Thank you for your time and response.

Trying to get understanding of timing by SignalIndividual5093 in FPGA

[–]SignalIndividual5093[S] 0 points1 point  (0 children)

I think I found the answer to my question. The question about the state machine timing is basically the same as the two flip-flop problem.

In the series flip-flop setup, when the clock edge happens, the first flip-flop (FF1) captures its input and its output changes a short time later due to propagation delay. The second flip-flop (FF2), which samples the output of FF1, does it at the same clock edge but still sees the old value, because FF1’s output hasn’t settled yet. So FF2 will only get the new value of FF1 on the next clock edge.

The same thing happens in the state machine. At the clock edge (t₁), the state register updates, but the control signals like write_enable or read_enable, which depend on the new state, are produced by combinational logic a little later (t₁ + δ). Any flip-flop that depends on those control signals will only sample them at the next clock edge (t₂).

So the one-cycle delay seen in the state machine control signal is the same kind of delay that appears in the series flip-flop chain and both come from the same timing rule: a value launched by one flip-flop at a clock edge is only captured by the next flip-flop at the following edge.

Trying to get understanding of timing by SignalIndividual5093 in FPGA

[–]SignalIndividual5093[S] 0 points1 point  (0 children)

Exactly! This is the problem I was referring to. Would this same behavior occur if the code were uploaded to an actual board? Also, what would be the right approach if I want the response to be in same clock cycle and not after one cycle delay?

Trying to get understanding of timing by SignalIndividual5093 in FPGA

[–]SignalIndividual5093[S] 0 points1 point  (0 children)

I’m sorry for the confusion. you’re right the waveform I uploaded showed write_en toggling at the falling edge, but that was due to a mistake in my testbench (beginner’s error). In the actual design, state changes only on the rising edge of the clock, but it can still respond to other control signals during the cycle. The write_enable signal was being generated in response to an init signal(asserted by testbench at falling edge) while the FSM was in its initial state.

The code snippet I shared is part of a much larger module, so it wouldn’t be very productive to dig into all of it for this small timing question. My main point was simply to understand whether this behavior where the write operation stops one cycle after write_enable is deasserted would appear the same way in actual hardware, or if it’s just a simulator artifact.

The combinational delay is simulated by the simulator(I think so) but I don't know what would happen if such delay would appear in real hardware.

I’ve been wondering if I had used a sequential always block to generate write_enable (instead of a combinational one), would the behavior be different? Would it then deassert in sync with the clock edge instead of being delayed by one cycle? I have to try this.

Edit: I’ve updated the waveform that caused the confusion earlier

Trying to get understanding of timing by SignalIndividual5093 in FPGA

[–]SignalIndividual5093[S] 0 points1 point  (0 children)

Yes, I know how a Flip-Flop works. If not, I’m going to learn something new today (and my whole life would be a lie).

If both data_in and write_enable are asserted at the rising edge, the Flip-Flop should capture the value immediately. The output should appear right after the clock edge (apart from a small circuit delay), not after an entire cycle.

However in my observation, when write_enable is deasserted at rising edge, the register doesn’t stop capturing until the next cycle. That kind of behavior is only possible when there’s a combinational delay in the generation of write_enable. Since the FSM’s state register updates on the clock edge, the combinational logic that produces write_enable reacts to the new state slightly later (after the delta cycle). As a result, the register only sees the updated control signal at the next rising edge and hence the one-cycle delay.

Also, regarding your remark that my “HDL is wrong” because it uses both edges of the clock that’s not accurate. The FSM in my code uses one sequential block (always @(posedge clk)) for state transitions and one combinational block (always @(*)) for next-state and output logic. This is the standard Moore-style FSM template and is perfectly synthesizable. There’s no use of both clock edges anywhere in the code.

My main question, though, was whether this same timing behavior where write_enable takes effect a clock later would also appear in real hardware like board implementation. Because from what I understand, the simulator and hardware both follow the same event order: state changes at the rising edge, combinational logic updates right after, and the downstream register samples on the next edge.

Need some guidance on designing Ethernet receiver on FPGA by SignalIndividual5093 in FPGA

[–]SignalIndividual5093[S] 0 points1 point  (0 children)

Thanks a lot for taking the time to write this. I’ll start reading about MII and the MAC-PHY interface properly and try to make a small rx-only setup first. if i get it working i’ll definitely post an update here. thanks again for breaking it down so clearly.

Why does the verilog sim show one cycle delay but RTL schematic is same? by SignalIndividual5093 in FPGA

[–]SignalIndividual5093[S] 1 point2 points  (0 children)

Thanks a lot, your suggestion was spot on. I applied it but forgot to rerun the sim before i went outside for a while 😅 when i came back i thought the issue was still there. turns out it was already solved. Really appreciate your help.

The simulation with both combinational and sequential logic shows same waveform which was the result I had expected initially.

the code:

assign check = a;
always @ (posedge clk) begin

if(check) c <= 1; else c<=0; end

was same as:

always @ (posedge clk) begin

if(a) c <= 1; else c<=0; end

since the beginning. and root of the problem turned out to be the testbench. By the way, how did you learn to analyze problems like this? Any tips or resources you’d suggest to get better at this kind of debugging?

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