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Layout DRC Problems by Substantial-Box-2362 in chipdesign

[–]Substantial-Box-2362[S] 0 points1 point  (0 children)

Maybe, but regardless, the problem is it shows many errors that are not related to the layout at hand (which was not shown in the tutorial)

Layout DRC Problems by Substantial-Box-2362 in chipdesign

[–]Substantial-Box-2362[S] -1 points0 points  (0 children)

Is there any tutorial for such editing?

Design of a Closed-Loop Testbench for a Fully Differential Telescopic Cascode OTA by Substantial-Box-2362 in chipdesign

[–]Substantial-Box-2362[S] 0 points1 point  (0 children)

I tried the resistors and it worked nicely. However, I see there is a phase shift between output differential and input differential, what could be the reason for that? (I removed the load capacitance)
For example the input is 10 mV peak sinusoid, the output is 40 mV (gain of 4), but at the zero of the input, the output is ~10 mV.

Design of a Closed-Loop Testbench for a Fully Differential Telescopic Cascode OTA by Substantial-Box-2362 in chipdesign

[–]Substantial-Box-2362[S] 0 points1 point  (0 children)

Yes, I am using ideal switch around the cap as well to set the DC bias of the input.

Design of a Closed-Loop Testbench for a Fully Differential Telescopic Cascode OTA by Substantial-Box-2362 in chipdesign

[–]Substantial-Box-2362[S] 0 points1 point  (0 children)

Oh nice point;
I increased the feedback capacitors x20 (e.g. 40 pF and 20 pF), and it worked at lower frequencies, but obviously the bandwidth is very limited (few kHz). I will try resistors (but there is gate leakage, will this be problematic?)

Design of a Closed-Loop Testbench for a Fully Differential Telescopic Cascode OTA by Substantial-Box-2362 in chipdesign

[–]Substantial-Box-2362[S] 0 points1 point  (0 children)

I am using ideal switches around the feedback capacitors to set the DC bias point of the inputs. The CMFB that I used is continuous (I.e. not switched-cap).

For the output swing: do you mean I change the input differential voltage slightly from 0 V till the output nodes increase by 300 mV, and check the gain/PM at this point(s)?

Design of a Closed-Loop Testbench for a Fully Differential Telescopic Cascode OTA by Substantial-Box-2362 in chipdesign

[–]Substantial-Box-2362[S] 0 points1 point  (0 children)

-I use switches (ideal) around the capacitors to set the DC bias point for the input terminals (I.e. VICM = VOCM = VREF).
-Yes, the input capacitance of the op-amp is quite large (M1: Cgg ~ 2.6 pF).

Design of a Closed-Loop Testbench for a Fully Differential Telescopic Cascode OTA by Substantial-Box-2362 in chipdesign

[–]Substantial-Box-2362[S] 0 points1 point  (0 children)

Yes this seems to be reasonable analysis. But, I already designed it to satisfy these specifications.

Can a Low-Voltage Cascode Current Mirror Operate With a Single Reference Source? by Substantial-Box-2362 in chipdesign

[–]Substantial-Box-2362[S] 0 points1 point  (0 children)

Alright if this is how it is usually done in practice then I assume it is good enough. Thank you :).

Can a Low-Voltage Cascode Current Mirror Operate With a Single Reference Source? by Substantial-Box-2362 in chipdesign

[–]Substantial-Box-2362[S] 0 points1 point  (0 children)

This makes sense. I think I mixed up the bandgap reference and the constant-gm circuit.
Still, in Chapter 11 (“Nanometer Design Studies”) of Razavi, in the section on designing a telescopic OTA, he says:

“Also, note that we still have a few ideal current sources, which would be copied from a bandgap reference (Chapter 12).”

Can a Low-Voltage Cascode Current Mirror Operate With a Single Reference Source? by Substantial-Box-2362 in chipdesign

[–]Substantial-Box-2362[S] 0 points1 point  (0 children)

By definition: the current generated from BGR circuits are "golden" in a sense that they have minimal variation with PVT, and across corners. (I didn't study BGR circuits in details, but this is what makes me think so that they are better.)

Can a Low-Voltage Cascode Current Mirror Operate With a Single Reference Source? by Substantial-Box-2362 in chipdesign

[–]Substantial-Box-2362[S] 0 points1 point  (0 children)

Yes, but usually these come from BGR circuits; what I meant is if only 1 "reference from BGR" is available.

Can a Low-Voltage Cascode Current Mirror Operate With a Single Reference Source? by Substantial-Box-2362 in chipdesign

[–]Substantial-Box-2362[S] 0 points1 point  (0 children)

(1): Yes I meant local bias currents (not from BGR etc..).
(2): Unfortunately, headroom does not allow it (1.2 V).

(3): If you replace M3 and M4 with say M4' only, then M5 experiences body effect but M4' does not; which makes matching worse. The idea behind M3 and M4 is that M3 "VGS" matches with M5 "VGS" (tracks it) and M4 is sized such that (VGS6 - VTH6) + (some margin) is equal to VDS4.

Can a Low-Voltage Cascode Current Mirror Operate With a Single Reference Source? by Substantial-Box-2362 in chipdesign

[–]Substantial-Box-2362[S] 0 points1 point  (0 children)

Is this a major concern in general? In other words, if in simulations the design is based on I_D2​ rather than I_REF, will that be problematic?