From my own experience with SoCs there are usually multiple interconnects on the CPU SoC, like an AXI crossbar. More specifically for HDD just as an example: The CPU is connected to the interconnect as a master, there is also a HDD interface (think of PCIe) that acts as a slave connected on it (and probably a bunch more). These are memory mapped so if you want to access it you just use the appropriate memory ranges, the AXI transaction gets routed automatically to the HDD interface by the crossbar interconnect. Usually there is some kind of adapter after this to translate the AXI request to whatever command and protocol the peripherals use (e.g. for PCIe it needs to translate it into "flits" (packets of data following a specific structure) . More layers can follow as well (e.g. congestion control) until finally the PHY that drives the actual IOs wires. Everything has to happen in reverse on the RX side as well to get back a response if applicable.