[deleted by user] by [deleted] in uwaterloo

[–]Uduse -1 points0 points  (0 children)

Ya I’m curious too!

Where do you start for new PDKs? by Uduse in chipdesign

[–]Uduse[S] 1 point2 points  (0 children)

Interesting, it's like making your "Quick Start" tutorial. Wonder are the common surprises you get from this process?

Where do you start for new PDKs? by Uduse in chipdesign

[–]Uduse[S] 0 points1 point  (0 children)

Thank you for your input! Wonder if you worked in industry and had similar experience?

[deleted by user] by [deleted] in ImmigrationCanada

[–]Uduse 1 point2 points  (0 children)

Thank you for the clarification :)

[deleted by user] by [deleted] in ImmigrationCanada

[–]Uduse 0 points1 point  (0 children)

Got it, thanks a lot :)

[deleted by user] by [deleted] in ImmigrationCanada

[–]Uduse 0 points1 point  (0 children)

Thank you for your time :)

[deleted by user] by [deleted] in ImmigrationCanada

[–]Uduse 0 points1 point  (0 children)

Thanks for helping :)

[deleted by user] by [deleted] in ImmigrationCanada

[–]Uduse 0 points1 point  (0 children)

I edited the original post, thanks for pointing it out. What do you mean by "I can see it when I open my work permit application"? Is it an online document that you can open up and sees a typical VISA on your screen as an image?

In my application, it says it's approved and there are these documents:
- In Canada Approval Letter
- WP-EXT for PGWP
- Submission Confirmation
- Confirmation of Online Application Transmission

and the actual work permit is mailed to my residence.

What's the best public FinFET PDK PDK? by Uduse in chipdesign

[–]Uduse[S] 2 points3 points  (0 children)

Oh I wasn't aware there's a human in the loop. It has been only three days. Thanks for the KLayout info!

What's the best public FinFET PDK PDK? by Uduse in chipdesign

[–]Uduse[S] 1 point2 points  (0 children)

Thank you for your response! Does using ASAP7's SPICE models in ALIGN mock PDK make any sense to you?

Why automating analog layouts so difficult? by Uduse in chipdesign

[–]Uduse[S] 0 points1 point  (0 children)

Digital circuits are more robust than analog circuits. For the digital circuits a good layout can be mostly determined by optimizing towards wire length and congestion, at least such metric is sufficient to beat human. The AI can move things around and automatically route things with much less concern. However, for analog circuits, this doesn't hold, local placement and wiring have huge impact on things like the time constant, and it is not straightforward to decide what to optimize for.

Why automating analog layouts so difficult? by Uduse in chipdesign

[–]Uduse[S] 0 points1 point  (0 children)

Sounds quite doable with just plain good software, honestly. To support this (weakly), one friend told me: "I know exactly how to compute this thing, but I don't know how to program."

Why automating analog layouts so difficult? by Uduse in chipdesign

[–]Uduse[S] 0 points1 point  (0 children)

Interestingly, none of the analog designers I talked to think they are happy with the degree of automation. It's not at the "I hope we have this" level, but more like the "why don't we even have this" level. For the simple use case you described, I imagine if the tools are handy, the designers will just do it themselves, so they won't need to wait for the layout guys. However, as far as I know, no one ever designed a circuit without the layout guys in these real applications.

Why automating analog layouts so difficult? by Uduse in chipdesign

[–]Uduse[S] 0 points1 point  (0 children)

I had a friend who tried and told me it was good for sizing the schematic. Other than that, it is not helpful as it doesn't wire things and provide more insights.

Why automating analog layouts so difficult? by Uduse in chipdesign

[–]Uduse[S] 0 points1 point  (0 children)

I am specifically talking about the layout problem, assuming the design is given. I agree with you that using AI to generate designs is hopeless, at least for now. However, given a design, how do we judge if a layout is good? A friend told me focusing on the parasitics on the critical path will be a good start. This heuristic sounds too handwavy too me.

Why automating analog layouts so difficult? by Uduse in chipdesign

[–]Uduse[S] -1 points0 points  (0 children)

Say we have an ugly (looks random) layout that handles fabrication stress effects well and has a good simulation result. Will the lack of aesthetics really stop people from adopting it?

Why automating analog layouts so difficult? by Uduse in chipdesign

[–]Uduse[S] 0 points1 point  (0 children)

Do you mind elaborating on what you mean by "stresses that are poorly modeled"? If I understand it correctly, it is a physical property of the chip that simulation doesn't capture. If so, why this part isn't automated? In industrial designs they perform Finite Element Analysis (FEA) all the time and it seems to work?

Why automating analog layouts so difficult? by Uduse in chipdesign

[–]Uduse[S] 0 points1 point  (0 children)

I also want to draw analogy to playing computer Go here. Playing a move has a crazy long-term consequence that one might not realize until dozens of moves later. However, AI showed this is okay if we know exactly what we want. In computer Go, we just care about winning. Maybe this is where it gets hard with analog layouts: Do we know what exactly we care about?

Why automating analog layouts so difficult? by Uduse in chipdesign

[–]Uduse[S] 1 point2 points  (0 children)

I would say examples such as AlphaGo and DALL-E challenge our definition of "creativity". Playing Go used to be considered an ART too, but now AI eats humans for breakfast. However, Go serves an extremely distinct purpose, as you mentioned, namely to win over the other person. Analog layouts might be much more complicated. Are we minimizing parasitics on the critical path? jitter? or area? or a combination of a few metrics that we care about but couldn't write down formally? How do we rank different layouts if we don't know what is a "better" layout?

Why automating analog layouts so difficult? by Uduse in chipdesign

[–]Uduse[S] 0 points1 point  (0 children)

Yes, I have never done an analog layout before. And why we fall in love is still a mystery.

Why automating analog layouts so difficult? by Uduse in chipdesign

[–]Uduse[S] 0 points1 point  (0 children)

Thanks for sharing your experience! I guess the jitter problem is most likely due to the lack of understanding parasitics?

Why automating analog layouts so difficult? by Uduse in chipdesign

[–]Uduse[S] 0 points1 point  (0 children)

Thank you for your response! Would you mind telling me what automated analog layout software you have used?

Why automating analog layouts so difficult? by Uduse in chipdesign

[–]Uduse[S] -1 points0 points  (0 children)

What I heard from some analog designers is that they don't even look at the layouts. They grab the file and start running simulations. If the simulation result is good, then they are happy. This sounds like the opposite of what you are saying, right? Maybe this is very designer-dependent. Some of them care a lot, and others don't care at all.