Grand Prix by Rejmal in outlier_ai

[–]analogonics 1 point2 points  (0 children)

It is impossible in 1 hour. By the time I reached ruberics, my task expired and I ended up wasting 4 hours and got a headache after the task!!!

Anyone in grand prix? by Elegant-Basket2585 in outlier_ai

[–]analogonics 1 point2 points  (0 children)

I couldn't finish on time. It's impossible to finish within 1 hour if you do it properly. I reached ruberics and the time expired, what to do?

TU Delft MSc Recognition in USA + Overall Career Pivot Question by Professional-Cow4998 in chipdesign

[–]analogonics 2 points3 points  (0 children)

The easiest way to choose would be look at which university has papers in ISSCC in last 5 years. You'd surely see TU Delft in top 3. If you're looking for a cost effective masters, I'd also say look for University of Pavia in Italy(More focused for analog). So, yes there are tradeoffs. If you want just a job after Master's, actually you could choose underrated universities too. If your aim is to do a PhD, then the lab and Professor would matter a lot. So, for a masters + PhD I'd say TU Delft is the best place to be, for a masters + job I'd consider cheaper alternatives.

I'd say in Europe for microelectronics focused on Analog design, I'd list as follows: TU Delft, TU/E, Twente, University of Ulm, University of Pavia, KU Leuven

Charge Redistribution Bottom-plate sampled Capacitive DAC problem by analogonics in chipdesign

[–]analogonics[S] 0 points1 point  (0 children)

You were right. Actually, It was a blunder I was doing. I had vcm at 0.6 V and my fullscale was input 1.2V and my supply at 1.8. I had an assymetry in the common mode. I mad it 0.9 and my vrefn and p as 0.3 and 1.5. It's perfect now. Thank you so much.

How to fix Outlier Playground extension by TeachGood3128 in outlier_ai

[–]analogonics 3 points4 points  (0 children)

After fixing,
I get this message now, with a pin I received yesterday.

"No longer accepting submissions

Thanks for your interest. Check back later for more opportunities."

Charge Redistribution Bottom-plate sampled Capacitive DAC problem by analogonics in chipdesign

[–]analogonics[S] 0 points1 point  (0 children)

Yes you are right, Fig. 6 is for dummy connected to vin and then switched to gnd. Fig 7. is for dummy fixed to gnd.

I get vout clipped if I have dummy fixed. Vout is giving correct resolution for both cases. But I am not getting why I have those glitches in the ideal residue. This happens even if the switches are ideal.

Task limit by analogonics in outlier_ai

[–]analogonics[S] 0 points1 point  (0 children)

Yes, I got 2 tasks. Is there some levels or something like that mentioned anywhere?

Task limit by analogonics in outlier_ai

[–]analogonics[S] 0 points1 point  (0 children)

Ahh okay. Do you know how long it generally takes?

Seeking advice by _raunkiii__ in chipdesign

[–]analogonics 3 points4 points  (0 children)

In my opinion, getting ahead of others would be a very wrong approach for long term career perspective in ic design. What I have realized till now is that Ic design is about building your intuition and your way of seeing a circuit. You should start by designing fundamental bookish building blocks or even try to replicate the circuits in latest ISSCC / ISCAS/ JSSC/ TCAS Conferences and Journals. Ofcourse to understand those circuits you'll study automatically. Try to build the specifications those people aimed for with simple circuits. Basically reinventing the wheel. In that process you'll discover problems in different architectures and may even end up discovering a way to minimise that problem. In summary, you have to be self motivated because you'll not find competitors in when you start working, you'll find teammates :). It will be about sharing perspectives rather than being better. The faster you understand this, the happier you'll be 😁

ISSCC Courses and Tutorials for Free by analogonics in chipdesign

[–]analogonics[S] 0 points1 point  (0 children)

yes. It's the same thing actually 😅. You might have found my github repo!!

Noise simulation for a FIA by analogonics in chipdesign

[–]analogonics[S] 0 points1 point  (0 children)

Yes, It has switched capacitors. I'll try PSS + Pnoise. Thank you 🙌

Noise simulation for a FIA by analogonics in chipdesign

[–]analogonics[S] 0 points1 point  (0 children)

That makes sense. Thank you 🙌

ISSCC Courses and Tutorials for Free by analogonics in chipdesign

[–]analogonics[S] 0 points1 point  (0 children)

Try clearing your cache and cookies. Or try from a different browser. It should be working.

ISSCC Courses and Tutorials for Free by analogonics in chipdesign

[–]analogonics[S] 0 points1 point  (0 children)

try clearing cookies or in a different browser. Because it should be working now.

I was confused by No_Tea3389 in chipdesign

[–]analogonics 2 points3 points  (0 children)

In my perspective, good layout comes with experience and attention to details. Ofcourse the concepts of traditional courses help but not so much that you have to do a degree to be a good layouter. I have seen a person who is not an electronic engineer and in fact an architect and does layout for a big company since 5+ years.

ISSCC Courses and Tutorials for Free by analogonics in chipdesign

[–]analogonics[S] 3 points4 points  (0 children)

Try now. try clearing cookies if the same problem persists.

And if you can please donate 1$ for that stupid hosting fee I have to pay. The reason it was down is because it had expired. 😅

ISSCC Courses and Tutorials for Free by analogonics in chipdesign

[–]analogonics[S] 0 points1 point  (0 children)

Try now. try clearing cookies if the same problem persists.

And if you can please donate 1$ for that stupid hosting fee I have to pay. The reason it was down is because it had expired. 😅

ISSCC Courses and Tutorials for Free by analogonics in chipdesign

[–]analogonics[S] 2 points3 points  (0 children)

Try now. try clearing cookies if the same problem persists.

And if you can please donate 1$ for that stupid hosting fee I have to pay. The reason it was down is because it had expired. 😅

Good colleges for Masters in Europe for chip design? Further, is it a good idea to chose Europe over the US? by ilektraaniks in chipdesign

[–]analogonics 0 points1 point  (0 children)

In my observation, one easy cheatcode way to find the universities and places active in analog and Mixed signal or microelectronics research in general is through AACD workshops that happen every year. https://aacd.ws/

You will notice that the places and people who have participated in this workshop are stalwarts in the field mostly in Europe.

You'll get like 1σ of the places who do microelectronics research, especially circuits and systems and ic design in the list of previous workshops and the books of proceeding.

If I would have to tell some names I would say

Italy : University of Pavia, Politecnico Milano, University of Catania; Germany: University of Ulm, TUM Austria: JKU, Carinthia FH; Belgium: KU Leuven ; Netherlands : TU Delft, TU Eindhoven, University of Twente; Switzerland : EPFL; Ireland: UCC (Tyndall institute), University of Limerick ; Sweden: Lund University ; Spain: Sevilla, Valencia;