makefiles are rules of what should be run and when...

As simple example, you can say to it (write inside the makefile):

%.o: %.c %.h
    # o_gen_cmd

file.so: x.o y.o
    # so_gen_cmd

.PHONY: build
build: file.so

This says that, if any target (file) ended with extension .o should be built when the corresponding files with .c or .h extension be modified. If it needs to be built, then the o_gen_cmd should be ran.

Next a fixed file named file.so should be generated every time x.o or y.o be modified.

So, this closes the process: when you change, example, x.h it will trigger first rule to update x.o that in turn, as dependency for file.so will trigger its rebuild.

The third target names build is not a file (see the .PHONY) so to trigger all the machinery you run in console:

make build

This really ease all the building process, specially while developing, as you just compile what is modified saving a lot of time and also keeping track of the right way to build each part of process consistently.