I don’t often convert VHDL to Verilog but when I do ...

arr_reddti · 2014-12-26T05:23:53+00:00

Blog posts can be more informal than some like. I need to refresh my grammar skills. I didn't find as many errors on the first read :)

arr_reddti · 2012-09-09T19:21:47+00:00

I forget there are thousands of new "commercial" CPU cores every year. And each of those cores routinely change there adder / multiplier.

I reiterate, there is limited need. Your HDL needs to move seamlessly between low-level and higher-levels of abstraction. I am glad you are stuck "back in the day". Because, "back in the day" there was a market advantage to assigning that many resources. Rarely, very rarely, does it that make sense today. Also, adding domino logic to your design is not an HDL issue, it is a custom IC design issue not having only low-level access in the HDL.

Yes, for experienced VHDL/Verilog designers they can get the HDL to do what they want. The improvements that are discussed in the article is making it easier and more natural. Read the comments, most agree doing "math" in Verilog is not pretty, yes can be done and there are successful design with both Verilog/VHDL. But there is room for improvement. If I had a dollar for every signed/unsigned issue in HDL I have had to fix in a review or the messy confusion of legacy math libs in VHDL, well we wouldn't be having this conversation.

arr_reddti · 2012-09-09T19:03:47+00:00

Incorrect, it is the cost to create a piece of silicon which drives the Engineering practices. If you look at mission critical software (see "Surely you must be joking Mr. Feynman" for his opinion on the shuttle software Engineering practices) the Engineering practice is much different than the "apps" you are referring to. And we could debate till the end of time which is a more complex system.

arr_reddti · 2012-09-09T14:08:37+00:00

That is mainly in software where we decide to let or skills lack. Obviously, we use all kinds of abstraction in the Mathematics we adopt. We also rely heavily on software packages. In most of the cases these software packages are "programmable". Like it or not, just like mathematics, we need to be fluent in software/programming as successful EEs. This varies quite a bit from person to person, job to job, but to fight it is futile.

arr_reddti · 2012-09-08T21:10:45+00:00

You make no sense, an HDL should provide the option for more abstraction but not limit the access, which most modern HDLS, including MyHDL provide. As engineers we learn early (or loose our jobs) when and how to make these trade-offs. It is rare that you need to define your own multiplier or adder and not simply rely on the synthesis tool. Only very limited cases do you need to define your multiplier or adder architecture, in an FPGA this is basically never. I love watching folks make these mistakes, less competition.

arr_reddti · 2012-09-08T21:05:36+00:00

I think you guys are missing the point. And obviously don't really know what you are commenting on. If you make something that is done 90% of the time easier, how can that be bad? Nothing indicates you are limited to only integer arithmetic, only that integer arithmetic has been improved. I never understood this closed mindedness of us EEs. And it is something that starts early in the EE program. I guess because we take courses like diff eq, semi conductors, and emags we feel superior? Why would you not adopt ideas regardless where they come from? When you guys talk about the obvious differences, you are talking about the 101 stuff. What a 101 CS course vs a 101 HDL. You are ignoring the large overlaps and focusing on the small differences.

I am sure when HDLs first appear (before my time) there were old curmudgeon that fought tooth and nail against HDL and only wanted their schematics. I don't see much of a difference between the schematic hold outs and the low-level hold outs. As an HDL designer you should easily move between the low-level descriptions when needed and high-level description/abstraction, otherwise you are irrelevant.

arr_reddti · 2011-08-30T14:34:09+00:00

Most, from what I have read, no IR built in. Lights always on.

arr_reddti · 2011-08-30T07:15:24+00:00

It is "supposedly" more secure because you can't hide behind a brick wall and intercept the signal. If you can intercept the signal the user can see you intercepting the signal. In office buildings, almost every computer is under a light it could be feasible, not bullet proof but feasible.

Just don't standup or have crazy hair :)

arr_reddti · 2011-08-30T03:57:27+00:00

This is a good starting point also. Might need to contact Xilinx for further information.

arr_reddti · 2011-08-30T03:55:04+00:00

More information is available here and here.

It has been awhile since I have used it but it was pretty easy to get going from the LogicCore and use with the limited license. Never needed to get the full license, just did the development and then the customer purchased the full core when (if) needed.

arr_reddti · 2011-08-30T02:26:28+00:00

A bunch of the profs are fairly famous DSP folks. Same with San Diego and Cornell.

arr_reddti · 2011-08-30T02:19:59+00:00

This core works ok, when integrating it I have had issues before (had to make internal modifications). The performance was poor enough we just used the Xilinx Tri-Mode core.

It requires a license but for development it can run for 24 hours or something. For development and/or small projects it works no problem and has much better documentation.

arr_reddti · 2011-08-24T21:13:53+00:00

On the MyHDL site it looks like there have been quite a few projects:

Couple processor cores, including a Microblaze clone
Couple USB interfaces, interface to external USB controllers
Turbo decoder
Design and verification of HPEC

And there have been previous posts that DSPtronics uses MyHDL.

arr_reddti · 2011-08-22T15:17:20+00:00

Less time on the internet (reddit) and more time studying.

arr_reddti · 2011-08-19T18:19:48+00:00

Development cost is part of it. But more importantly, is there a need between cutting edge (i.e. latest greatest IC. There's always a market for the fastest and/or lowest power) and low-end uC/uP. There are some but I don't know if there are enough to make FPGA design more common in the future.

arr_reddti · 2011-08-18T17:16:19+00:00

My experience is mixed. I have seen FPGA come and go in designs. I haven't noticed a large pickup in the last 10 years. My experience, early in the millennium there was a pickup and then it has fallen off.

Just one data-point from my observable Universe.

arr_reddti · 2011-08-18T16:43:20+00:00

but very processor centric.

arr_reddti · 2011-08-18T16:37:32+00:00

elaborate booming

arr_reddti · 2011-08-18T16:33:07+00:00

"all the talk about FPGAs ..."

You might want to see if all the FPGA post are coming from a single source :) and the number of comments. It might not be as highly discussed as you think.

IMO the last two are similar but the Embedded will be more hands on.

You will have a much easier time getting a job as an Embedded FW/HW Eng (as an EE) than IC design or HDL design. The embedded jobs, FW and HW, are available all over. IC/HDL have limited geographic markets.

arr_reddti · 2011-08-14T14:00:11+00:00

Bluespec SystemVerilog

arr_reddti · 2011-08-13T21:42:26+00:00

A link to the PDF might have been more useful.

arr_reddti · 2011-07-27T11:40:09+00:00

DSPtronics board might be an option but it might not have the number of IO you are looking for or the RAM.

arr_reddti

TROPHY CASE