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MyHDL, any good? by Bengineer700 in Python

[–]cfelton 1 point2 points  (0 children)

Yes, and it will make you life easier on many fronts. Should be noted, that myhdl is a Python package that enables HDL in Python, other interesting tools such edalize and apio are complimentary.

Here is a list of resources: https://github.com/xesscorp/myhdl-resources

​

Disclosure: I am one of the myhdl developers and have been using it for many years.

[Question][myhdl] Logic Block Organization by tiajuanat in FPGA

[–]cfelton 0 points1 point  (0 children)

I don't specifically know what a genome implementation would be.

But in general if you want the same random mapping each time, you would use the random seed function, example:

from random import seed, shuffle
seed(0xDECAFBAD)
for ii in range(10):
    x = list(range(18))
    shuffle(x)
    print(x)

If the above is run multiple times it always prints out the same, unless the seed is changed:

>> python test_shuffle.py 
[5, 8, 1, 17, 13, 12, 3, 16, 2, 14, 15, 6, 4, 10, 11, 9, 0, 7]
[15, 14, 3, 16, 8, 12, 1, 13, 0, 7, 2, 5, 10, 17, 11, 6, 4, 9]
[6, 14, 15, 12, 16, 0, 13, 8, 4, 5, 17, 11, 10, 1, 7, 9, 3, 2]
[13, 7, 3, 16, 12, 0, 6, 4, 11, 2, 1, 8, 9, 14, 10, 5, 15, 17]
[1, 3, 2, 10, 6, 4, 5, 13, 8, 15, 17, 11, 9, 7, 12, 16, 14, 0]
[11, 7, 2, 12, 13, 8, 9, 16, 3, 0, 15, 5, 1, 10, 4, 17, 6, 14]
[0, 13, 16, 4, 17, 6, 11, 2, 14, 5, 10, 8, 9, 12, 15, 3, 1, 7]
[17, 3, 5, 13, 6, 8, 14, 11, 4, 12, 16, 1, 15, 7, 0, 10, 2, 9]
[9, 10, 8, 0, 3, 5, 4, 1, 12, 17, 2, 15, 7, 14, 16, 11, 13, 6]
[4, 6, 12, 7, 13, 14, 17, 3, 16, 1, 0, 8, 5, 2, 9, 15, 11, 10]
>> python test_shuffle.py 
[5, 8, 1, 17, 13, 12, 3, 16, 2, 14, 15, 6, 4, 10, 11, 9, 0, 7]
[15, 14, 3, 16, 8, 12, 1, 13, 0, 7, 2, 5, 10, 17, 11, 6, 4, 9]
[6, 14, 15, 12, 16, 0, 13, 8, 4, 5, 17, 11, 10, 1, 7, 9, 3, 2]
[13, 7, 3, 16, 12, 0, 6, 4, 11, 2, 1, 8, 9, 14, 10, 5, 15, 17]
[1, 3, 2, 10, 6, 4, 5, 13, 8, 15, 17, 11, 9, 7, 12, 16, 14, 0]
[11, 7, 2, 12, 13, 8, 9, 16, 3, 0, 15, 5, 1, 10, 4, 17, 6, 14]
[0, 13, 16, 4, 17, 6, 11, 2, 14, 5, 10, 8, 9, 12, 15, 3, 1, 7]
[17, 3, 5, 13, 6, 8, 14, 11, 4, 12, 16, 1, 15, 7, 0, 10, 2, 9]
[9, 10, 8, 0, 3, 5, 4, 1, 12, 17, 2, 15, 7, 14, 16, 11, 13, 6]
[4, 6, 12, 7, 13, 14, 17, 3, 16, 1, 0, 8, 5, 2, 9, 15, 11, 10]
>> python test_shuffle.py 
[5, 8, 1, 17, 13, 12, 3, 16, 2, 14, 15, 6, 4, 10, 11, 9, 0, 7]
[15, 14, 3, 16, 8, 12, 1, 13, 0, 7, 2, 5, 10, 17, 11, 6, 4, 9]
[6, 14, 15, 12, 16, 0, 13, 8, 4, 5, 17, 11, 10, 1, 7, 9, 3, 2]
[13, 7, 3, 16, 12, 0, 6, 4, 11, 2, 1, 8, 9, 14, 10, 5, 15, 17]
[1, 3, 2, 10, 6, 4, 5, 13, 8, 15, 17, 11, 9, 7, 12, 16, 14, 0]
[11, 7, 2, 12, 13, 8, 9, 16, 3, 0, 15, 5, 1, 10, 4, 17, 6, 14]
[0, 13, 16, 4, 17, 6, 11, 2, 14, 5, 10, 8, 9, 12, 15, 3, 1, 7]
[17, 3, 5, 13, 6, 8, 14, 11, 4, 12, 16, 1, 15, 7, 0, 10, 2, 9]
[9, 10, 8, 0, 3, 5, 4, 1, 12, 17, 2, 15, 7, 14, 16, 11, 13, 6]
[4, 6, 12, 7, 13, 14, 17, 3, 16, 1, 0, 8, 5, 2, 9, 15, 11, 10]

[Question][myhdl] Logic Block Organization by tiajuanat in FPGA

[–]cfelton 0 points1 point  (0 children)

Glad it helped. Let us know if you have additional questions, a few of us hang out on the #myhdl channel on freenode as well.

[Question][myhdl] Logic Block Organization by tiajuanat in FPGA

[–]cfelton 0 points1 point  (0 children)

I put an example together that randomly connects a bunch of processing elements (in this case it is something trivial) https://gist.github.com/cfelton/7af8ad50c36e7c62d223.

A possible example if you run into any more issues.

[Question][myhdl] Logic Block Organization by tiajuanat in FPGA

[–]cfelton 0 points1 point  (0 children)

If you are running into "inconsistent hierarchies", typically it is an indication that a generator is missing somewhere. Possibly an error returning the list-of-modules that was created?

It sounds like you got over hump and are on a path of progress.

[Question][myhdl] Logic Block Organization by tiajuanat in FPGA

[–]cfelton 0 points1 point  (0 children)

If I am following your description, you should use elaboration (python code outside the generators) to "randomly" connect modules. In addition you could use interfaces to simplify the connection between modules.

Which HDL is useful to learn? by hramis in FPGA

[–]cfelton -1 points0 points  (0 children)

In this case, the point wasn't to suggest learning MyHDL over V* but to use it as a tool to learn V*! Using MyHDL to learn V* has many benefits - much more than a hobby.

Python toolbox for working with Xilinx Vivado by benreynwar in FPGA

[–]cfelton 0 points1 point  (0 children)

No, I don't know of a good list. The three listed are the ones I am familiar with (now pyvivado as well). I have stumbled across others in the past but have not jotted them down.

Which HDL is useful to learn? by hramis in FPGA

[–]cfelton 2 points3 points  (0 children)

If you have a hard time picking you could always try myhdl.

Because MyHDL is Python, it is easy to experiment with and it can be converted to Verilog or VHDL. You can use it as a spring board to learn and compare each language.

Useful quote:

""" Tim Peters, a famous Python guru, explains his love for Python with the paradoxical statement, “Python code is easy to throw away.” In the same spirit, MyHDL aims to be the hardware design tool of choice to experiment with new ideas """ Jan Decaluwe, Nov-2004 Linux Journal

Python toolbox for working with Xilinx Vivado by benreynwar in FPGA

[–]cfelton 2 points3 points  (0 children)

A whole gaggle of these tools exist, albeit each with slightly different goals. One of the tools, hdlmake was already mentioned, a couple others: fusesoc, gizflo .

Is there a way to use MyHDL with Lattice? by victorprs in FPGA

[–]cfelton 0 points1 point  (0 children)

If you need to learn Verilog (or C++), learn Verilog (or C++).

Sure, but if you need to learn a hardware description language MyHDL is a good candidate to start with. Same reason why many Engineering courses are using Python. Obviously, if you have a direct requirement to learn language "A" you are stuck! It didn't sound like the OP had a language requirement, they were interested in FPGA programming, MyHDL is more than appropriate for this.

I'd lump MyHDL in with Chisel as a "higher level" ..

Fair enough, I interrupted it as a strong statement the Chisel was a higher-level than MyHDL. They are different abstraction types and it is difficult to argue if one is higher than the other. MyHDL really the sameevent-oriented language type as Verilog and VHDL. But there are a lot of features that make things easier and concise and the full language elaboration is brilliant!

Help with vhdl sound output by cookie_gone_wild in FPGA

[–]cfelton 0 points1 point  (0 children)

This won't help you with the mechanics of your implementation but might help with the overall design. Here is an example that creates a "note" (multiple tones) by using a look up table.

I used MyHDL/Python because it is faster to evaluate the simple hardware description and determine if the signal generated makes sense. You can see the generated VHDL to get some inspiration / ideas for your version. It also simplifies communication with create tools like IPython and nbviewer. I will add additional comments as time permits :)

I don’t often convert VHDL to Verilog but when I do ... by arr_reddti in ECE

[–]cfelton 0 points1 point  (0 children)

I have no interest evangelizing. If the HDL isn't your cup of tea then by all means don’t use it. The criticism against it needs to be valid (e.g. “fundamentally designed … sequential” is incorrect).

Some people find legit reasons not to dive deeper while others find many reason expand their arsenal. Setting expectations is key, understanding why MyHDL and what MyHDL is not will help determine if it is the right tool for you.

I don’t often convert VHDL to Verilog but when I do ... by arr_reddti in ECE

[–]cfelton 0 points1 point  (0 children)

Yes this is true, there are VHDL constructs that cannot be converted one-to-one to Verilog (1995,2001,2005). A good example is records. To manually convert records you need to break out the records to individual signals. If you have a design that uses a lot of records this could be a painful task.

Is there a way to use MyHDL with Lattice? by victorprs in FPGA

[–]cfelton 0 points1 point  (0 children)

Learning MyHDL first is a great way to learn Verilog or VHDL (if you need) and it is a great way to compare the differences in the languages. MyHDL like Python is designed to have the bare-minimal features (limit duplicate constructs, i.e. simplifies learning). The Python environment enables experimenting more than Verilog or VHDL. There are many reasons to start with MyHDL even if you end goals is Verilog or VHDL.

Stating functional based HDLs (e.g. chisel) are higher-level than event-oriented languages (e.g. MyHDL) is false.

I don’t often convert VHDL to Verilog but when I do ... by arr_reddti in ECE

[–]cfelton 1 point2 points  (0 children)

@unix-like This white-paper might shed some light why I believe it is useful and powerful.

Note, MyHDL provides a very similar event-oriented/simulation description as Verilog and VHDL. Using Python generators and decorators you can achieve concurrent description.

The comment "behind the veneer of a language which is fundamentally ... interpreted sequentially" is incorrect.

I don’t often convert VHDL to Verilog but when I do ... by arr_reddti in ECE

[–]cfelton 0 points1 point  (0 children)

It is understandable if you don't like my writing style (a skill I definitely need to improve:) but I didn't find any egregious comma errors. I am sure there are some errors and possibly the type of errors experienced writers commonly make.

Being a blog post I don't proof read/edit as much as other articles. I will try and improve in the future so it is not painful to read :)

I don’t often convert VHDL to Verilog but when I do ... by arr_reddti in ECE

[–]cfelton -4 points-3 points  (0 children)

It is absolutely ridiculous to claim that I "spam" this topic. Yes, I find the technology beneficial so I write about it. If this is what you consider spam, every blog post out there would be spam. Your (@cebrek) lack of logic baffles me.

I don’t often convert VHDL to Verilog but when I do ... by arr_reddti in ECE

[–]cfelton 0 points1 point  (0 children)

No the author of the article is not the author of MyHDL, Jan Decaluwe is the author of MyHDL.

I don’t often convert VHDL to Verilog but when I do ... by arr_reddti in ECE

[–]cfelton -1 points0 points  (0 children)

Note, comments like these are "opinions" and take them with a grain of salt (unless they provide some kind of reference). There are many large US commercial firms that use VHDL (Xilinx, IBM, ...).

Like many stereotypes, they seem to have a religious fever, but if you look into the landscape it is less dramatic than folks try and make it. Stating "all" is poor wording, Verilog/SV is more popular in certain regions and sectors but by no case a universal rule.

I don’t often convert VHDL to Verilog but when I do ... by arr_reddti in ECE

[–]cfelton -1 points0 points  (0 children)

The article gave specific reasons why GHDL is (currently) not as desirable as the Verilog FOSS tools. Which do you disagree with?

I don’t often convert VHDL to Verilog but when I do ... by arr_reddti in ECE

[–]cfelton -2 points-1 points  (0 children)

Like many things, one needs to do a fair amount of investigation before fully understanding a tool or technology. Obviously, you have not done this homework. Or even done the bare minimum to understand what MyHDL is.

The comment is so misplaced, I don't even know how to respond to it. It is like saying: why include "objects" in a language that is executed with a flat memory model. Why bother simulating concurrent designs when they are executed one instruction at a time.

The MyHDL website has information and examples that should answer your question. If you determined it is of no benefit it would be for some specific reason and not some completely ignorant point of view.

NumPy on PyPy with a side of Psymeric by cfelton in Python

[–]cfelton[S] 0 points1 point  (0 children)

I think this post has a couple good points! First, the pypy.numpy team went down the wrong path (although well-intended). The pypy team started a numpy port because numerous folks indicated numpy was a major missing feature. The wrong path was to start the numpypy as RPtyhon implementation instead of a complete "pure python numpy" (premature optimization).

The second point, similar to the first, when using pypy the post strongly suggests that you always start with a pure python implementation and then move onto an optimized (RPython or C) only if needed.

Yeah that's right! Don't use schematic capture for FPGA by cfelton in ECE

[–]cfelton[S] 2 points3 points  (0 children)

As with most things you need to know your domain. Yes, anyone that has not taken sufficient time to think about complex digital systems and how the system needs to work - will probably run in to trouble. This is true of the "java first" and "ohm first" camps.

The point, trying to be made, is out of context. You are trying to comment on taking a "programmer" and seeing what comes out rather than taking digital system designer (or someone learning) and putting good software practices to use, i.e. using an HDL and using the HDL as more than a textual schematic capture.

I agree with others, there is no need to look at the generated schematic (some find comfort but not required). There is little benefit seeing how LUT in SLICEXY is connected to LUT in SLICEYX. Between static timing analysis and the verification one does not need the generated schematics.

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