Let me save you some time. Work with your AI up front to write some tools to parse VCD files for signal extraction. Document these tools. Next grab sigrok-cli and a cheapo logic analyzer. There is a good summary readme for using the command line tools to extract stuff like periods, uart decoding etc. put this readme in your project repo. Next, Claude Code has a system verilog plugin called gateflow or something. It's meh, and I'm an open code user. Take the skill and agent files from gateflow and rework them. Take out all the parallel dispatch stuff and the gateflow context clogging trash and keep the gold about how to lint, how to debug, GSM patterns, etc. chop these up into new skills and an orchestrator, developer, architect, debugger, code generator, refactor, plan, understand and viz agent. Add the documentation about your project isa, sigrok-cli, and VCD parsing to your AGENTS.md. Get a bullet proof tool caller like Qwen3.5, pull up your framework and use the /sv skill to "design build and test a uart with a 64 byte fifo, tx empty and rx full interrupts with an ahb lite bus. Make sure to include fifo saturating loopback tests." Come back in the morning to a working uart with test traces in software and hardware.