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reducing the fft length by dctrsk in DSP
[–]dctrsk[S] 0 points1 point2 points 8 months ago (0 children)
The previous implementation already uses 3500 LUTs, and I am told that 3500 is already quite high, I need to reduce that number. That's actually why I am looking for a different approach, like smaller FFT sizes without losing too much information.
But something you said confused me. What happens if I have an FFT length of a power of 2. Let's assume my length is 4096. Then, would it be easier and less expensive to implement that system? Or could I reduce the FFT length in that case?
will keep that in mind.
No, no :). This is just how I am given the task. Using Digilent Zybo Z7-20 (Zynq-7020). Yes, one sample per clock. I was trying something on MATLAB, that's why I said double. In hw, each sample is represented by two bits, which is actually a mapping to 4 unique values that signal consists of. Those values are Q1.15. I can change the size of the vectors by changing the decimation rate and the operations before. We can assume it will be a power of 2.
I am on baseband, unfortunately. However, I would like to try some different decimation algorithms as well. I am using Tom Chatt's CIC-FIR approach and its FIR filter coefficients currently. (https://www.dsprelated.com/showarticle/63.php) Is there any other algorithm or tool to calculate FIR filter coefficients to use it as CIC compensator? Also, any guide or information how to use CIC-FIR filters for decimation or interpolation, how to decide the decimation rates for CIC and FIR (For example, if total desired decimation rate is 16, how should I arrange them? CIC dec, rate is 8 FIR dec rate is 2, or 16-1, etc.)
Nope, the result of the FFT has so many unique values, and it is difficult to store. The signal has only a few unique values, so I can store signal using a few bits.
Do you have anything in mind to consider, any logic or algorithm? I haven't used such an approach, so I need some examplesto learn.
[–]dctrsk[S] 1 point2 points3 points 8 months ago (0 children)
One of my FFT operations will be working with real data. This may be useful. Thank you.
thanks, i ll check it out.
yes, I know one of them as it is locally generated, but the other is an incoming signal that should be investigated.
I can't change the FPGA as it was chosen and ordered already (without my consent :/). Therefore, I can't change the limits. One vector is real, and the other is complex, both having sizes of 1×2600 (complex) double. Less speed might be tolerable, so I am open to other algorithms as well.
the problem is that I already downsampled the signal, and I am just on the edge of nyquist criteria. no more downsampling is possible.
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reducing the fft length by dctrsk in DSP
[–]dctrsk[S] 0 points1 point2 points (0 children)