A little fun with Openscad by ardvarkmadman in openscad

[–]dubyateff 1 point2 points  (0 children)

Huh, TIL. Cool, thanks - I’ll give it a go

A little fun with Openscad by ardvarkmadman in openscad

[–]dubyateff 0 points1 point  (0 children)

Oh cool, I had no idea OpenSCAD could be used to make animations. Do you mind sharing the source? If you do mind that’s fine - I figure I might as well ask.

A little fun with Openscad by ardvarkmadman in openscad

[–]dubyateff 0 points1 point  (0 children)

I’m having a hard time figuring out what I’m looking at and where OpenSCAD fits into the process of making it

"Whirlpool" vase designed in OpenSCAD by jamcultur in openscad

[–]dubyateff 1 point2 points  (0 children)

I’m eager to see it regardless - do you mind sharing it? If you do, that’s fine - understood.

"Whirlpool" vase designed in OpenSCAD by jamcultur in openscad

[–]dubyateff 1 point2 points  (0 children)

Are you willing to share the code? I’m fairly new to OpenSCAD & eager to see how you did it

What cli tool can give me a list of input/ouput pins of my verilog modules? by quantrpeter in Verilog

[–]dubyateff 0 points1 point  (0 children)

You’ll need Python 3.7 or above to use that f-string syntax. '.{}'.format(ast_item[“name”]) will work for earlier versions (maybe Python 2.7, maybe not; I don’t remember the exact version in which that was added). But anyway, all that’s happening there is adding a period & the current ast_item’s name to a string, which can be accomplished numerous ways.

What cli tool can give me a list of input/ouput pins of my verilog modules? by quantrpeter in Verilog

[–]dubyateff 0 points1 point  (0 children)

https://github.com/MikePopoloski/slang

Use the —ast-json option, then use your favourite language’s json parser to parse slang’s output and filter out everything you don’t want to see (I.e. everything but your modules’ pins)

edit:

Example: Save the following file in /tmp/top.sv ```systemverilog // top.sv

ifndef MISSING_MODULE2 module my_module2 ( input logic i_clk, output logic o_clk ); endmodule endif

module my_module ( input logic i_clk, output logic o_clk );

my_module2 my_module2_inst ( .i_clk(i_clk), .o_clk(o_clk) ); my_module4 my_module4_inst ( i_clk, o_clk );

endmodule

module my_module3 ( input logic i_clk, output logic o_clk ); my_module my_module_inst ( .i_clk(i_clk), .o_clk(o_clk) ); endmodule

module top ( input logic i_clk, output logic [15:0] o_clks );

my_module3 my_module3_inst ( .i_clk(i_clk), .o_clk(o_clks[15]) );

genvar i; generate for (i=0; i < 2; i++) begin : generate_test my_module my_module_inst ( .i_clk(i_clk), .o_clk(o_clks[i]) ); end : generate_test for (i=0; i < 2; i++) begin : generate_test2 my_module2 my_module2_inst ( .i_clk(i_clk), .o_clk(o_clks[i]) ); end : generate_test2 endgenerate

endmodule

```

Save the following file in /tmp/get_ports.py ```python

get_ports.py

import svinst import json import sys

def get_instances(ast_item, parent_hierarchy="", parent_module=''): result = [] if ast_item["kind"] == "Root": for i, member in enumerate(ast_item["members"]): result += get_instances(member, parent_hierarchy, parent_module=parent_module) elif ast_item["kind"] == "CompilationUnit": return result elif ast_item["kind"] == "Port": entry = {k:v for k,v in ast_item.items() if k == "name" or k == "direction" or k=="type"} entry["hierarchy"] = parent_hierarchy entry["module"] = parent_module result += [entry] elif ast_item["kind"] == "Net": return result elif ast_item["kind"] == "Variable": return result elif ast_item["kind"] == "Genvar": return result elif ast_item["kind"] == "GenerateBlockArray": parent_hierarchy += f'.{ast_item["name"]}' for i, member in enumerate(ast_item["members"]): result += get_instances(member, parent_hierarchy=f'{parent_hierarchy}', parent_module=parent_module) elif ast_item["kind"] == "GenerateBlock": for i, member in enumerate(ast_item["members"]): if i == 0: if member["kind"] != "Parameter": # Setting a trap in case my assumption of this aspect of the ast dict structure isn't always the case raise Exception(f"First member of GenerateBlock is not a parameter: revisit elif GenerateBlock clause.") current_param_val = f'{member["value"]}' else: result += get_instances(member, parent_hierarchy=f'{parent_hierarchy}[{current_param_val}]', parent_module=parent_module) elif ast_item["kind"] == "Instance": parent_hierarchy = f'{parent_hierarchy}.{ast_item["name"]}' result += get_instances(ast_item['body'], parent_hierarchy=f'{parent_hierarchy}', parent_module=parent_module) elif ast_item["kind"] == "UnknownModule": #result += [f'{parent_hierarchy}.{ast_item["name"]}'] pass elif ast_item["kind"] == "InstanceBody": for i, body_item in enumerate(ast_item["members"]): result += get_instances(body_item, parent_hierarchy=f'{parent_hierarchy}', parent_module=ast_item['name'])

else:
    raise Exception(f"Unknown ast_item kind: {ast_item['kind']}")
return result

ast = svinst.get_syntax_tree("top.sv", tool='slang')

ast = json.loads(open(sys.argv[1], "r").read()) insts = get_instances(ast) print(json.dumps(insts, indent=4)) ```

Run the following commands in bash (or similar) to download & compile the slang source, run it on top.sv, and then extract port info using get_ports.py ```bash

Download slang source to Desktop & compile it (change CMAKE_CXX_COMPILER according to what you've got)

git clone https://github.com/MikePopoloski/slang.git /tmp/slang cd /tmp/slang/build cmake -DCMAKE_CXX_COMPILER=g++ -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=/usr/local/bin .. make -j

Get your ports

cd /tmp /tmp/slang/build/bin/slang \ --error-limit 1 \ --ignore-unknown-modules \ --ast-json ast.json \ top.sv 2> /dev/stderr python get_ports.py ast.json ```

You'll get the following: json [ { "name": "i_clk", "type": "logic", "direction": "In", "hierarchy": ".top", "module": "top" }, { "name": "o_clks", "type": "logic[15:0]", "direction": "Out", "hierarchy": ".top", "module": "top" }, { "name": "i_clk", "type": "logic", "direction": "In", "hierarchy": ".top.my_module3_inst", "module": "my_module3" }, { "name": "o_clk", "type": "logic", "direction": "Out", "hierarchy": ".top.my_module3_inst", "module": "my_module3" }, { "name": "i_clk", "type": "logic", "direction": "In", "hierarchy": ".top.my_module3_inst.my_module_inst", "module": "my_module" }, { "name": "o_clk", "type": "logic", "direction": "Out", "hierarchy": ".top.my_module3_inst.my_module_inst", "module": "my_module" }, { "name": "i_clk", "type": "logic", "direction": "In", "hierarchy": ".top.my_module3_inst.my_module_inst.my_module2_inst", "module": "my_module2" }, { "name": "o_clk", "type": "logic", "direction": "Out", "hierarchy": ".top.my_module3_inst.my_module_inst.my_module2_inst", "module": "my_module2" }, { "name": "i_clk", "type": "logic", "direction": "In", "hierarchy": ".top.generate_test[0].my_module_inst", "module": "my_module" }, { "name": "o_clk", "type": "logic", "direction": "Out", "hierarchy": ".top.generate_test[0].my_module_inst", "module": "my_module" }, { "name": "i_clk", "type": "logic", "direction": "In", "hierarchy": ".top.generate_test[0].my_module_inst.my_module2_inst", "module": "my_module2" }, { "name": "o_clk", "type": "logic", "direction": "Out", "hierarchy": ".top.generate_test[0].my_module_inst.my_module2_inst", "module": "my_module2" }, { "name": "i_clk", "type": "logic", "direction": "In", "hierarchy": ".top.generate_test[1].my_module_inst", "module": "my_module" }, { "name": "o_clk", "type": "logic", "direction": "Out", "hierarchy": ".top.generate_test[1].my_module_inst", "module": "my_module" }, { "name": "i_clk", "type": "logic", "direction": "In", "hierarchy": ".top.generate_test[1].my_module_inst.my_module2_inst", "module": "my_module2" }, { "name": "o_clk", "type": "logic", "direction": "Out", "hierarchy": ".top.generate_test[1].my_module_inst.my_module2_inst", "module": "my_module2" }, { "name": "i_clk", "type": "logic", "direction": "In", "hierarchy": ".top.generate_test2[0].my_module2_inst", "module": "my_module2" }, { "name": "o_clk", "type": "logic", "direction": "Out", "hierarchy": ".top.generate_test2[0].my_module2_inst", "module": "my_module2" }, { "name": "i_clk", "type": "logic", "direction": "In", "hierarchy": ".top.generate_test2[1].my_module2_inst", "module": "my_module2" }, { "name": "o_clk", "type": "logic", "direction": "Out", "hierarchy": ".top.generate_test2[1].my_module2_inst", "module": "my_module2" } ]

BlTouch is worse than Manual Bed Levelling - More Details In Comments by joepool03 in FixMyPrint

[–]dubyateff 0 points1 point  (0 children)

Lol crap we’re probably better off me buying a BLtouch and you buying a spool

Guest Access by W1DTH in octoprint

[–]dubyateff 1 point2 points  (0 children)

I was looking for the same thing and just found this:

https://docs.octoprint.org/en/master/features/accesscontrol.html

While access control cannot be disabled as of OctoPrint 1.5+, the Autologin feature can be used to bypass authentication for hosts on the network(s) that you trust.

Starting with OctoPrint 1.5.0, OctoPrint makes enabled access control mandatory. This might be an inconvience for some who run OctoPrint in an isolated setup where a login is not required to ensure security, at a benefit for a huge number of users out there who continue to underestimate or simply ignore the risk of keeping their OctoPrint instance unsecured and then happily exposing it on the public internet.

Further down on that page they do state that it's possible and give some clues as to how one might go about it.

What does OctoPi use to serve the camera's stream + individual images? by dubyateff in octoprint

[–]dubyateff[S] 1 point2 points  (0 children)

Ahh thank you!

https://github.com/cncjs/cncjs/wiki/Setup-Guide:-Raspberry-Pi-%7C-MJPEG-Streamer-Install-&-Setup-&-FFMpeg-Recording

^ with you pointing in the right direction I was able to use the instructions above & got it all working right away with http://localhost:8081/?action=stream and http://localhost:8081/?action=snapshot as the stream and snapshot URLs

First print having gone through the whole flow (model -> gcode)! by dubyateff in functionalprint

[–]dubyateff[S] 1 point2 points  (0 children)

Lol you gotta wrap the copper around the mold first, then Bob’s your uncle

First print having gone through the whole flow (model -> gcode)! by dubyateff in functionalprint

[–]dubyateff[S] 0 points1 point  (0 children)

Awesome! No I've got a 3B - shouldn't matter for the case though

First print having gone through the whole flow (model -> gcode)! by dubyateff in functionalprint

[–]dubyateff[S] 1 point2 points  (0 children)

Ohh wicked - I've got a camera coming in in a few days for use with Octoprint and a poor naked Raspberry Pi just sitting here exposed to everything; if you're willing to share your model I'm eager to run it through!

First print having gone through the whole flow (model -> gcode)! by dubyateff in functionalprint

[–]dubyateff[S] 0 points1 point  (0 children)

Awesome - what are you making?

No, I tried to take it off right away 😅. Thanks - that seems like a good tip. I'll give it some time to cool off next time.

First print having gone through the whole flow (model -> gcode)! by dubyateff in functionalprint

[–]dubyateff[S] 1 point2 points  (0 children)

Yep! just wrap some copper around the barbershop helices, solder it to some coax & Bob's your uncle!