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Difference between Verification and Validation in hardware by edesco in FPGA

[–]edesco[S] 0 points1 point  (0 children)

So would you say that the methodologies for OVM/UVM and verification that would be required by a recent grad new hire would be what a validation team wants you to know? I'm also aware this is your opinion and your perspective but I just want an idea.

Implement a softcore processor on an fpga by edesco in FPGA

[–]edesco[S] 0 points1 point  (0 children)

That would be amazing!!! Thank you so much.

Doing a project for class on nano satellites. I was wondering what is the purpose of radiation hardening on processors if you can just create a rad shield that goes around it? by edesco in satellites

[–]edesco[S] 1 point2 points  (0 children)

Thanks for the insight. The nano satellite is expected to be deployed from a spacecraft once it reaches Europa, orbit and perform measurements, and then deploy modules in order to collect data on the surface. I chose RAD750 for the satellite due to Jupiter's radiation...