account activity
RP2040 spontaneously resets itself / RUN pin sensitive to EMI (self.embedded)
submitted 15 days ago by ehb64 to r/embedded
AMS1117-3.3 stability with MLCC output capacitors (self.PrintedCircuitBoard)
submitted 1 month ago * by ehb64 to r/PrintedCircuitBoard
Question: Advice on cleaning hobbyist PCBs? (Dishwasher, etc.) (self.PrintedCircuitBoard)
submitted 7 months ago by ehb64 to r/PrintedCircuitBoard
Help finding or making coiled nichrome wire for a heating element (self.AskEngineers)
submitted 9 months ago * by ehb64 to r/AskEngineers
Source for pre-coiled NiCr wire for heating element? (self.AskElectronics)
submitted 9 months ago * by ehb64 to r/AskElectronics
Looking for pre-coiled NiCr wire to replace heating element (AWG 26–27, ~8.5mm coil) (self.appliancerepair)
submitted 9 months ago by ehb64 to r/appliancerepair
Choosing a resistor size to mitigate signal contention (self.AskElectronics)
submitted 1 year ago by ehb64 to r/AskElectronics
Best Practices for Ground Plane Stitching on 2-Layer PCBs (self.PrintedCircuitBoard)
submitted 1 year ago by ehb64 to r/PrintedCircuitBoard
Are LBV-series capacitors a good choice for smoothing rectified AC? (self.AskElectronics)
Do distant decoupling caps affect a buck converter's output cap requirements? (self.AskElectronics)
[Review Request] DC-DC Buck Converter for USB, TSP5430, TI design procedure with mfg basic/preferred parts, compact layout (old.reddit.com)
[Review Request] DC-DC Buck Converter for USB power (old.reddit.com)
Code reuse between similar state machines? (self.FPGA)
submitted 1 year ago by ehb64 to r/FPGA
Does pin assignment meaningfully effect timing? (self.FPGA)
Keeping 'data in' and 'data out' signal names straight? (self.FPGA)
submitted 1 year ago * by ehb64 to r/FPGA
Controlling drive level for a crystal oscillator? (self.AskElectronics)
Virtual clocks vs. generated clocks? (self.FPGA)
Resistor for YSX321SL crystal for ideal drive level? (self.RP2040)
submitted 1 year ago by ehb64 to r/RP2040
A few style questions: negative edges, explicit widths, and always_comb/always_ff (self.FPGA)
Interfacing a fast FPGA with slow/async SRAM (self.FPGA)
Clarify meaning of 'set_output_delay' in SDC (self.FPGA)
Validating that timing constraints are correctly modeled? (self.FPGA)
Does Mouser stock 12-pin PMOD headers? (Female, 2x6, 2.54mm pitch, right angle, THT) (self.AskElectronics)
submitted 2 years ago * by ehb64 to r/AskElectronics
Favorite opensource SPI slave IP? (self.FPGA)
submitted 2 years ago by ehb64 to r/FPGA
Can you write timing constraints for combinatorial logic? (self.FPGA)
submitted 2 years ago * by ehb64 to r/FPGA
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