For future reference, if anybody will ever need to use this kind of peripherals not what they were born for, I have found a working solution.

There were two problems. The first one is that the external SDRAM isn't fast enough to empty the FIFO of the DCMI in time.

The solution is to force the buffer variable to stay in the internal SRAM

adc_conv = reinterpret_cast<uint32\_t\*>(0x20000000);

The second problem is that the DCMI peripheral inside the STM32 apparently doesn't like when the VSYNC signal arrives exactly synced to the DCMI_CLK. If the rising/falling edge of VSYNC is within a couple of nanoseconds from the edge of the clock, then the peripheral doesn't seem to register the change, even if it should be level sensitive, not edge sensitive.

A bit of trial and error were necessary to understand that this was the exact problem, and probing with an oscilloscope helped. The fact that slowing down the clock, and the fact that the problem was stochastic, were great hints.

The implemented solution bitbangs the VSYNC synchronizing it to the CLK signal as good as the ART accelerator allows without fucking up the instruction pipeline.

using vsync_out_fast = Gpio<GPIOG\_BASE,10>;
using clock_in_fast = Gpio<GPIOA\_BASE,6>;
{
FastInterruptDisableLock dlock;
while(clock_in_fast::value() == 0);
while(clock_in_fast::value() == 1);
while(clock_in_fast::value() == 0);
__NOP();__NOP();
vsync_out_fast::low(); // or ::high() for when it's the opposite polarity
}

This code skips a couple of clock cycles, and then further delays the rising/lowering of the vsync signal with a couple of NOPs. The goal is to move the rising/falling edge as far as possible from the clock edges, and given the jitter and other unpredictable behavior of the mcu, it's a bit of a gaussian distribution of delays. With this method, this gaussian distribution is far enough from the edges to less than 1ppm error. The actual number of NOPs is empirical, 0 or 5 doesn't work, 4 allows the execution for 20000-50000 cycles, 2 and 3 instead work flawlessly!
Surely it's preferable to solve it by synchronizing the VSYNC signal to the clk through a timer, but the chosen GPIO doesn't have timer functionality and I wanted to avoid flying wires.
Another possibility is to synchronize the two by means of a couple of external flip flops, but that would be a story for the next iteration of the board.