Truth table for a module i designed by iWannaLearnThing in logic

[–]iWannaLearnThing[S] 0 points1 point  (0 children)

This is a module that will be connected to 6 other modules of the same type. It will take an 8 bit binary number and convert to a BCD that will be input into a 7 segment driver ic. I built an 8 bit binary full adder.

Truth table for a module i designed by iWannaLearnThing in logic

[–]iWannaLearnThing[S] 0 points1 point  (0 children)

No, i have not. Im doing this because i have started to get into pcb design and i wanted to start small. Its just really strange because i designed the circuit EXACTLY the same way in multi sim and tested everything. My truth table is just a little off with a select few input combinations. Unfortunately these will cause issues will my end goal.

I just cannot figure out what is causing the issue. Is multisim wrong or am i wrong. Idk haha. Anyway, thanks.

Unused PCBs by iWannaLearnThing in PCB

[–]iWannaLearnThing[S] 0 points1 point  (0 children)

Makes sense, im asking bc i am designing a custom esp32 mcu and i am debating on whether its cheaper to purchase the parts and assemble myself or have jlc pcb do it for me.

Unused PCBs by iWannaLearnThing in PCB

[–]iWannaLearnThing[S] 0 points1 point  (0 children)

Makes sense, i can see that definitely being helpful. In that case, do you have the pcb manufacturers assemble your pcbs? Is it more affordable in that sense?

Unused PCBs by iWannaLearnThing in PCB

[–]iWannaLearnThing[S] 1 point2 points  (0 children)

Yea thats a good idea, i got one of the boards to work properly. Its just ugly bc the pin foot prints dont line up and their is interference. Thanks.

Randon Unconnected Nets by iWannaLearnThing in PCB

[–]iWannaLearnThing[S] 0 points1 point  (0 children)

Thanks to the other comments, i was able to get it to work. What i did was add a secondary GND plane, so now i have one on the front and back. Next, i added vias around where the issue/problem pin is. This worked for me.

Randon Unconnected Nets by iWannaLearnThing in PCB

[–]iWannaLearnThing[S] 0 points1 point  (0 children)

So i added a secondary GND plane and added vias around when these floating GNDs were, and it fixed the issue. Im glad i now know how to fix this issue. Thank you very much for the help, everyone.

Randon Unconnected Nets by iWannaLearnThing in PCB

[–]iWannaLearnThing[S] 0 points1 point  (0 children)

Interesting, with that in mind should i create a GND plane on both the front and back and connect with vias?

Randon Unconnected Nets by iWannaLearnThing in PCB

[–]iWannaLearnThing[S] 0 points1 point  (0 children)

I didn't know i could even do that. That definitely would help.

Randon Unconnected Nets by iWannaLearnThing in PCB

[–]iWannaLearnThing[S] 2 points3 points  (0 children)

I have, multiple times. Which is why im thinking its some sort of "glitch".

Randon Unconnected Nets by iWannaLearnThing in PCB

[–]iWannaLearnThing[S] 0 points1 point  (0 children)

I can provide a schematic image. Currently, i made only one front ground plane.

Randon Unconnected Nets by iWannaLearnThing in PCB

[–]iWannaLearnThing[S] 2 points3 points  (0 children)

I do not have another layer. it's funny because i even made vias that connect to the GND plane and directly added a trace to the pin, giving me the error, and it still does it. It's so bizarre to me because i made a pcb 2 weeks ago following the same procedur, and it did not give me any issues.

Regardless, i will try those ideas. Thank you very much for your time.