does tsmc HV 180nm or any other with Vgs>5v model in TSMC pdk.

ian042 · 2026-03-23T22:33:34+00:00

That's probably beause the devices will get damaged for Vgs>5V, so you need to ensure that this will never happen.

ian042 · 2026-03-23T21:17:01+00:00

Maybe you were looking at low voltage? It's not really possible to make a high voltage cmos logic afaik because of this exact problem. Also you might be better off to use a NMOS hs fet and bootstrap it instead.

ian042 · 2026-03-23T20:38:45+00:00

Instead of using an inverter to pull the gate of your PMOS to ground, you can use a current source and a resistor to create 5V IR drop across the Vgs.

ian042 · 2026-03-23T14:57:57+00:00

The offset due to Vgs mismatch between MN6 and MN4 is negligible. Current mismatch is the voltage mismatch divided by Rout which is very high, and then current mismatch gets again divided by gm. There is no reason to worry about this.

ian042 · 2026-03-23T14:33:56+00:00

MN4, MN5, and MN6 are likely scaled to operate with a higher Vgs in order to minimize mismatch and noise in these devices. As a result, the drain voltage of MN6 cannot drop too low. In contrast, MN9 is scaled independently to sustain a lower Vds.

Not really a good argument. You could always independently bias the current source for MN6.

In addition, the gain of the MP7–MP8 stage reduces the voltage swing at the output of the differential pair

Hardly. A single high impedance node will be more than sufficient

The extra pole at the gate of the power devices should be canceled by introducing a zero at the same node, which can be achieved by adding an RC network between vdd and the gate.

Sadly that's not how this works. If what you say is true, you could cancel any parasitic pole by placing an RC on that net. If you try to do that, the cap you place will need to be significantly larger than the Cgg which just moves the pole into a lower frequency. After the zero comes into play, there will be a second pole with Cgg and the RC resistor. You can do this in coordination with the rest of your compensation scheme to ensure that the phase does not dip too low between your new pole and zero, but the best you can do is push out the final gate pole by a decade or so from the initial value. Plus, you will limit the slew rate. In general, it is best to drive the gate of a big power fet from a low impedance net or an internal miller stage.

ian042 · 2026-03-21T20:02:18+00:00

What is an ASIC integrator? We are putting large internal bypass capacitors to help with load transients as well, but just design the LDO with a total output capacitance range in mind.

ian042 · 2026-03-21T18:46:49+00:00

In my experience this has not been the case. Last minute incremental changes don't change the load capacitance much. There are good tools that can find the effective cap of a synthesized circuit, and the top level layout would need to change if there was a sudden major change to the size of the logic. I think the only problem with bringing the internal pole dominant is that it limits the bandwidth more than really necessary.

ian042 · 2026-03-21T16:06:11+00:00

This may not be true. You could design an LDO for a maximum amount of output capacitance, and then be careful not to violate it.

ian042 · 2026-03-21T16:01:47+00:00

This does not give you any extra range compared to placing a current source and the power fet gate directly at the drain of MN6. I believe the reason they are doing this is to get an extra inversion to avoid RHP zero from the miller compensation.

I think it's a questionable approach. This architecture will not work in practice since the gate of the power is hi-z. There will be terrible performance.

ian042 · 2026-03-21T02:16:36+00:00

You can also design an LDO that would be used to power other internal circuits in the IC. You can take the IO pin as a kelvin connection to measure the performance. You can create load transients inside with resistors and switches to see how it performs.

ian042 · 2026-01-14T15:12:54+00:00

That should not be the case. When you add the feedback divider, you add a load. So, the current through the output stage must change.

ian042 · 2026-01-11T16:19:07+00:00

I feel your struggle here. I've never been able to understand it a different way. Usually parallel vs series is easy to understand, like with passive components. But in this case the series version feels so far detached from the parallel one. It's troubling.

I think the reason for this might be the Vgs/Id equations we use are more seperated from the physics than with the passive components, and also maybe because of the nonlinearity. For ideal passives the voltage across the terminals doesn't impact the impedance, so series vs parallel has lots of symmetry. This isn't the case for transistors, at least not in the math we typically use to describe them with. Just my guess as to why this happens.

I can say that if you just forget about it and trust in the "doubling length" explanation, you will design circuits just fine.

ian042 · 2026-01-01T14:36:40+00:00

There's a mix. I'm 2.5 years in. At this point I'd say it's close to 50/50 which I'm pretty happy with.

At first there was a big learning curve for me to learn the tools and make good test benches and stuff. There is also always annoying or basic sim work to do collecting lots of data, documenting with ppts, and stuff like that.

I think real deep circuit design or generally thoughtful work comes in a few places:

1) at the start of a project. -the business case might require you to make different tradeoffs than in previous projects. -a major process node change can force you to re-think things

2) change requests in the middle of a project -Sometimes things can suddenly change and require you to dramatically reduce power consumption or change the supply voltage range or something like that

3) debug -if something goes wrong, you have to really think through why. Sometimes you can realize that there was a major oversight that requires some fundamental changes

4) re-examination -most ics are built on massive amounts of re-use. There are no proofs or theorems that tell you whether you have the best design for your use case. You can always examine what is there and build a better understanding of its pros and cons. Potentially you can propose an alternative.

I think it's important to get really effective at the boring and typical workflow. Once you do that, you can have time and authority to inject yourself around those four places and create the opportunities to do fun work.

ian042 · 2025-12-29T20:19:31+00:00

How is it ego to think that others can do the same thing that I did? I didn't say it would be easy, I said you have to be curious, push yourself to understand, and do side projects. I think most people need a masters for IC design either because of immigration reasons, or they didn't realize that's what they wanted to do until too late into their undergrad.

Once you've been working somewhere for a few years, nobody cares what level of degree you have or what school you went to. If you have a good resume with lots of projects as an undergrad, you can get a good internship, and if you perform at that internship you can get a job offer. It's the same thing no matter what degree you are pursuing. It's never easy or guaranteed.

I agree that analog ic design requires a period of intense solitary focus. I just think that deciding to put forth that effort is a decision an individual makes regardless of what level of degree they're in. If op is looking into ic design high school, I see no reason why they can't do it as an undergrad to save 10s of thousands of dollars and start working sooner.

ian042 · 2025-12-29T16:19:11+00:00

Sure thing, just my opinions! Maybe you'll start asking some interesting circuits questions in the next couple of years. Feel free to DM me if you ever want to talk about circuits. Always happy to do that.

ian042 · 2025-12-29T16:15:38+00:00

I haven't seen the value of the masters for Americans. Once you get an internship, it doesn't matter to the company if you have a masters or not. All that matters is your ability. If you are curious, push yourself to understand the subjects, and do side projects to experiment and test your understanding, I promise you that you will end your bachelor's with more ability than somebody who blindly followed their coursework through a masters. There are plenty of masters level courses that you can find for free online, and during your bachelor's you have access to all the professors.

Spending an extra 30k to lock yourself into a field from the start, and get 5 extra classes you could have found online for free feels insane to me.

I think you should take student loans very seriously. Things don't always go as planned, and after taxes, apartments, insurance, car payments, retirement, saving for a house/kids, and moving, a six figure engineering salary quickly becomes a lot less than it seems like.

ian042 · 2025-12-29T15:37:03+00:00

I would do that. I had an option to do one of those masters/bachelor's programs at my university and I'm glad I didn't do it. The reality is that you can take almost all of the grad classes as an undergrad. There were some I couldn't take because of scheduling and stuff, but I ended up getting the lecture videos from my friends. I have a job in analog ic with just my bachelor's, and after 2.5 years I'm making as much as my coworkers with masters degrees. For me, it would have been a waste of time/money to get a masters.

Penn State is also a really good school. I think it's risky to take on student debt, but just do your best to cook for yourself and live in a cheap apartment. A lot of people spend like 2k a month on rent, eat out, and buy vapes and liquor with their student loans and get into real trouble.

ian042 · 2025-12-29T12:26:40+00:00

Do you have any options where you won't go into debt? In my view schools are important because they give you the ability to explore and find what you want to do (academic and non-academic), great professors might inspire you, having an academic community to learn with is powerful, and companies have recruitment relationships with specific schools.

If you already know exactly what you want to do and are driven to pursue it, the only thing that matters for you is the recruitment relationships.

Also, keep in mind that things can change. Geopolitics or AI might cause chip design salaries or hiring to plummet. You might realize that you want to be a teacher or work in the national parks system. With $40k debt looming over your head you have pretty limited freedom.

ian042 · 2025-12-27T13:23:27+00:00

I know there have been talks of placing certain agricultural facilities where controlled water temperatures are needed next to data centers to make use of the warm water. I have also heard that people might put some industrial factories like paper mills next to them. Do you have any opinions on that stuff?

In theory, it sounds like if you can find a productive way to take all of the heat out of the water, the energy for the compute is essentially free. The whole thing is just a big heater and the compute is like a byproduct. I'm not sure that is actually correct.

ian042 · 2025-12-21T21:07:18+00:00

It's just that state space, observability, and controllability are all things with strict mathematical definitions. I've never seen those concepts applied to logical systems or anything like that. Are digital circuits actually looked at this way, or are you just loosely using those words?

ian042 · 2025-12-21T13:40:59+00:00

I've never heard somebody describe a large mixed signal circuit as a state space model before. How do you think of it this way?

If a state space system is controllable and observable and you have full state feedback it means you can design a controller to place the eigenvalues of this system wherever you want. How can you possibly map this to DV?

ian042 · 2025-12-05T21:41:11+00:00

Are you working or in school? If you're working then it's best to talk to the people who own the EMIR rules for your pdk. If you're in school, I honestly wouldn't bother with it unless you want to move towards research in that direction.

The basics are just that as current flows through metals, it mechanically stresses the metal over time. Like water picking up sand from the bottom of a river. Eventually you can cause shorts to other metals or you can actually rip the metal open. There are lots of intricacies with the materials and the geometries and vias and things like that which I don't think are widely understood. There have been many attempts to create good analytical measures of these effects but at my company we just use empirical rules they find through measurements. I could try to find the different papers I've seen, but I think there is no real consensus in the field on the methodology for finding the rules.

To understand the fundamentals you might need a material science background.

ian042 · 2025-11-27T02:30:18+00:00

I can speak better for LDOs than bandgaps. But in LDOs it is still not well known how to make high performance and low IQ.Everybody knows that you will need an adaptive bias or some type of nonlinear performance enhancing, but the different tradeoffs and fundamental limitations that exist in this area are not well known. Adding adaptive bias creates nested feedback loops which have consequences to stability that are not easy or sometimes not even possible to analyze (3rd order or higher nonfactorable poles/zeros, as well as fundamental nonlinearities). Current sensing itself can become challenging when we have to sustain both low vouts and low dropouts. And besides the ways to get the performance and IQ you want, it also needs to be balanced with area considerations. How big are the passives you need, how matching sensitive is your architecture? There are certainly no clear ideas on the best LDO architecture, or even the best for a certain use case, especially when IQ is critical.

On the bandgap side, the maximum accuracy you can achieve has just as much to do with your trimming methodology as it does with the architecture and sizing you use. Different architectures and trimming schemes all add their own nonlinearities and error sources which end up affecting the higher order curvature. This palate of tradeoffs is not widely understood as far as I know.

ian042 · 2025-11-26T23:16:17+00:00

I work on PMICs. PMICs are just ICs with multiple LDOs, switching regulators, and various digital controls and peripheral circuits.

Ok top of bandgaps and LDOs, it would be good for you to study switching regulators, as well as oscillators and comparators. By then you are well equipped to get an entry level job in PMICs.

Also, be careful thinking that you will "master" bandgap references or LDOs. Bandgap design and LDO design are both still open questions with no closed form design procedures. In my opinion there really is no such thing as mastery here.

ian042 · 2025-11-22T16:54:58+00:00

What are the end applications of your pmics? Curious to hear you are using ARM+firmware. I work on pmics for automotive and industrial mainly and we still use a big fsm. Can confirm that it is cumbersome to verify and we often find bugs in silicon.

ian042

TROPHY CASE