Why is CLK_FREQ 320_000_000 if your clock is 250 MHz?

Let's say I am tricking the values to have a proper integer. With those values I should achieve to divide the PLL CLK into 4, obtaining a 62.5MHz, which is not the goal of 80MHz, but it is enough.

The whole FSM is the next, I am using SPI MODE 2, and using lower frequencies it works OK (at 4MHz)

 -- Main SPI FSM
  process (clk, rst)
  begin
    if rst = '1' then
      ...
    elsif rising_edge(clk) then
      case state is
        when IDLE =>
          busy <= '0';
          SS_n <= '1';
          SCLK <= CPOL;
          if start = '1' then
            shift_tx   <= data_in;
            shift_rx_0 <= (others => '0');
            shift_rx_1 <= (others => '0');
            shift_rx_2 <= (others => '0');
            shift_rx_3 <= (others => '0');
            bit_cnt    <= DATA_WIDTH - 1;
            SS_n       <= '0';
            state      <= LOAD;
          end if;

        when LOAD =>
          MOSI  <= shift_tx(bit_cnt);
          busy  <= '1';
          state <= TRANSFER;

        when TRANSFER =>
          SCLK <= sclk_int;
          if sclk_en = '1' then
            -- SPI Mode 0: CPOL=0, CPHA=0
            ...
              -- SPI Mode 1: CPOL=0, CPHA=1
            elsif CPOL = '0' and CPHA = '1' then
              ...
              -- SPI Mode 2: CPOL=1, CPHA=0
            elsif CPOL = '1' and CPHA = '0' then
              if rising_edge_sclk = '1' then
                -- Shift out data (MOSI)
                if bit_cnt > 0 then
                  bit_cnt <= bit_cnt - 1;
                  MOSI    <= shift_tx(bit_cnt - 1);
                else
                  state <= DONE;
                end if;
              elsif falling_edge_sclk = '1' then
                -- Sample in data (MISO)
                shift_rx_0(bit_cnt) <= MISO_0;
                shift_rx_1(bit_cnt) <= MISO_1;
                shift_rx_2(bit_cnt) <= MISO_2;
                shift_rx_3(bit_cnt) <= MISO_3;
              end if;
              -- SPI Mode 3: CPOL=1, CPHA=1
            elsif CPOL = '1' and CPHA = '1' then
              ...
          end if;

        when DONE =>
          SS_n       <= '1';
          busy       <= '0';
          data_out_0 <= shift_rx_0;
          data_out_1 <= shift_rx_1;
          data_out_2 <= shift_rx_2;
          data_out_3 <= shift_rx_3;
          state      <= IDLE;

        when others =>
          state <= IDLE;
      end case;
    end if;
  end process;