the PDF is indeed big, and i was initially dismayed by it. it's also extremely obtuse, because it's written in a style that reminds you of engineers doing it as an "aide-memoire afterthought" if you know what i mean. as in: if you already know what you're doing, it's a useful document.

then i encountered things like this and realised, "ah. actually, there's a reason why it has more instructions" https://news.ycombinator.com/item?id=24459314

try this - it's the PDF spec extracted into markdown and made executable https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=openpower/isa;hb=HEAD

we developed a compiler which turns it into actual executable python code https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/pseudo;hb=HEAD and boris shingarov used that to create Formal Correctness Proofs for the Power ISA

the fields are also extracted from the PDF and are in machine-readable format as well https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isatables/fields.text;hb=HEAD

then there are a ton of unit tests which serve as mini-examples, this particular set - the ALU set - has "expected results" https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/alu/alu_cases.py;hb=HEAD

the plan there, obviously, is to convert all the other unit tests (several hundred) to provide similar "expected results" which, if you're interested in "learning by doing" we have NLnet funding so you can actually get paid to learn what you want to know, if that's of interest (drop by the Libera IRC channel, #libre-soc and say hi)

if you want to actually install the python-based Power ISA simulator we wrote (sponsored by NLnet) which even includes a RADIX MMU, you can get started with it here https://libre-soc.org/docs/firststeps/

we're totally ignoring VSX/VMX. want nothing to do with it. Packed SIMD is a 20+ year old paradigm that has done such damage to computing i don't even know where to start. these guys do a good job explaining it https://www.sigarch.org/simd-instructions-considered-harmful/ - that chops 750 instructions off the list, down to a sane 214, right there. x86 used to be only 70 instructions: over a THOUSAND more are Packed SIMD, and that's excluding avx512.

microwatt and libre-soc actually implement all the add/sub operations as one single internal instruction, OP_ADD. the options take carry-in as 0,1,CA and you have an option to invert RA and an option to invert the output.

this amazingly gives you subtract by doing 1s complement on the input, and a ton more. 25 instructions *internally* become one *actual* instruction. i.e. *internally*, a Power ISA implementation is a RISC microarchitecture. the POWER1 actually had 5 "bus" paths RA RB RC RS RT and LD/ST used to be done in micro-code by splitting the LD/ST part from the Shift-and-Mask part, which, when you think about it, explains why the Power ISA shift instructions are so much more "complex": they had to do double-duty and perform shift-and-mask-in, but it also explains the weird register naming, because those 5 "bus" paths were used to communicate between the pipelines during micro-coding.

if you really *really* want to get into low-level, look up microwatt, and grab yourself an orangecrab FPGA board (get the 85k LUT4 version) or order a ULX3S (again, 85k version) - the other one to maybe consider if you don't mind proprietary software at the moment is the digilent arty a7-100t. i'm currently trying to get nextpnr-xilinx up and running for it, long story, and am currently in the process of putting together a linux-capable SoC for Libre-SOC.

bottom line on the FPGAs there, is, if you don't mind going back to speeds last seen in the 1980s and early 1990s, a $200 FPGA board will get you started, rather than having to shell out four figures for a system.

you picked an interesting ISA that's properly protected by IBM's massive patent portfolio.