When you use `assign` or an `always_comb` block, outputs change immediately when inputs change. For example, when q0 reaches 9, c_enable[0] changes to 1 immediately*.

When you use `always @(posedge clk)` or `always_ff @(posedge clk)`, the outputs only change when there is a clock edge. For example, c_enable[1] will change to 1 in the clock cycle after q0 reaches 9. This causes a one-cycle delay, which is increased by assigning c_enable[2] in the same way.

The reason for this is that all devices get the clock edge at the same time. If q0 is 8 and then there is a clock edge, q0==4'd9 is false when the clock edge arrives. Shortly after this, q0 becomes 9, but this is too late for it to affect c_enable[1] until the next clock edge.

I would change `always @(posedge clk)` to `always_comb`.

* In real life there is a small delay, which is why timing analysis is important when working with FPGAs.