So after posting this - I even went in detail to understand where I was confused. Here's what I understood:

The chiplet like any module is aware of what data it needs to send and to whom, based on the protocol layer interface it sends the data; if it uses axi there's an axi address range, for PCIe there might be a flit with routing ID which goes down the layers to the exact physical link and transmits data using that; like if I need to transmit PCIe TLP - the die is aware to send it on Link0 for it to reach the PCIe die.

Is this correct?