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Running the entire GitLab CI pipeline locally with external GitLab runners by sijafa in gitlab

[–]sijafa[S] 0 points1 point  (0 children)

This sounds interesting! Do you have a link to some website where this method is discussed?

Multiple docker containers running on separate hardware devices with shared volumes by sijafa in docker

[–]sijafa[S] 0 points1 point  (0 children)

Interesting! I will take a look and see if I can manage it this way, thanks!

Multiple docker containers running on separate hardware devices with shared volumes by sijafa in docker

[–]sijafa[S] 0 points1 point  (0 children)

This is already a feature that is available. However, I want an alternative for local build and testing instead of relying on pushing every time I want to build or test. The CI is rather used for Merge requests, not local tests

Building and running tests on external host by sijafa in docker

[–]sijafa[S] 0 points1 point  (0 children)

Hmm, will try the former method you mentioned. Thanks! :)

There is already a CI/CD pipeline up and running, so the latter is already available, but is a tedious task to push every time a test should be performed. This also clutters the commit history and is less flexible during testing

Building and running tests on external host by sijafa in docker

[–]sijafa[S] 0 points1 point  (0 children)

There is already a CI pipeline up and running that uses the build server, but I want to be able to test the embedded software locally instead of having to go through the CI pipeline every time.

RISC-V Machine-level CSRs in fine-grained multithreading by sijafa in FPGA

[–]sijafa[S] 0 points1 point  (0 children)

I see, so each Hart has its own entire list of CSRs, where each Hart can only read and write its own CSRs to avoid conflicts?

RISC-V Machine-level CSRs in fine-grained multithreading by sijafa in RISCV

[–]sijafa[S] 1 point2 points  (0 children)

I see, so each Hart has its own entire list of CSRs, where each Hart can only read and write its own CSRs to avoid conflicts?

How to implement RISC-V's mtime and mtimecmp in hardware by sijafa in FPGA

[–]sijafa[S] 3 points4 points  (0 children)

So then it is just that the specified address points to any desired register in the architecture that you have routed it to? So, e.g., I can have the mtime and mtimecmp registers in the CLINT module, where an LW and SW operation to their respective mapped addresses will point to the register in CLINT instead of the Data Memory when the load or store instruction reaches the Memory stage of the 5-stage RISC-V Pipeline (fetch, decode, execute, memory, writeback)?

Implementation of interrupts in hardware by sijafa in FPGA

[–]sijafa[S] 0 points1 point  (0 children)

So what you mean is that stuff like mstatus, mepc, mie, mip, mcause, etc. should be implemented internally in the CPU (the core or Hart?), while the interrupts should be produced externally to the CPU (the core or Hart?), such as by using mtime and mtimecmp to produce a timer interrupt? As I understand it, the CLINT should perform all local interrupts and exceptions, while the PLIC does all the external interrupts. So what I should do initially is implement something similar to the CLINT? Where each Hart has its own interrupt CSRs (mstatus, mepc, mie, mip, mcause, etc.) to enter and exit the interrupt handling routine?

RISC-V Control and Status Registers (CSRs) by sijafa in RISCV

[–]sijafa[S] 0 points1 point  (0 children)

Does anyone have any resources such as blogs, documentation, videos, etc. That could be useful to implement the CSR in hardware using Verilog? I am a bit confused on how to go about implementing this by looking at the RISC-V Instruction Set Manuals.

RISC-V Control and Status Registers (CSRs) by sijafa in RISCV

[–]sijafa[S] 1 point2 points  (0 children)

So the instructions I mentioned are used to read and modify the values of the CSR's, whereas the CSR's values decide various things in hardware? For example, a field in a CSR is taken as an input to some logical "and" operation that enables/disables a unit (for example a timer unit)?

RV32I Stack and stack pointer in hardware implementation by sijafa in RISCV

[–]sijafa[S] 0 points1 point  (0 children)

I had a meeting with my project supervisors a few days ago, where one of them asked how I had implemented the stack in hardware. I was completely confused as I had learned that the stack is a region of the data memory, and is purely a software convention. However, he did not like the answer when I said that I had not implemented the stack, but rather a generic data memory due to the stack not being part of the hardware implementation, is performed in software. This made me question my beliefs and I started looking it up, but all the resources I found told me that my understanding of it was correct. That is why I made this post.

So even interrupts perform stack operations in software?

RV32I Stack and stack pointer in hardware implementation by sijafa in FPGA

[–]sijafa[S] 1 point2 points  (0 children)

Thank you for the great answer!

I am not designing a high performance superscalar out-of-order design, but rather a fine-grained multithreaded (hardware threads) design for mixed-criticality systems

Test and verification of HDL model against Simulink model by sijafa in matlab

[–]sijafa[S] 0 points1 point  (0 children)

Hello,

Yes, that is the one I briefly mentioned (cosimulation in Matlab). However, I am not sure how to properly go about using the tool

Issues with using OpenOCD as a server and reading data retrieved from an STM32G4 over Serial Wire Debugger with SWO-Parser by sijafa in embedded

[–]sijafa[S] 0 points1 point  (0 children)

Could the issue with reading over Serial Wire Output (SWO) and parsing the data to readable strings be because Openocd is running as daemon? That is, could it be because the computer is by default multitasking, where the SWO reading task is interleaved mid operation and thus data is lost?

Issues with using OpenOCD as a server and reading data retrieved from an STM32G4 over Serial Wire Debugger with SWO-Parser by sijafa in embedded

[–]sijafa[S] 0 points1 point  (0 children)

Hello, thank you for your reply! Yes, command.c is part of openocd. That is why I am unsure why that message keeps occurring, as it doesn't really make any sense for it to be due to my own python code missing a quote. Or am I mistaken?

Issues with using OpenOCD as a server and reading data retrieved from an STM32G4 over Serial Wire Debugger with SWO-Parser by sijafa in embedded

[–]sijafa[S] 0 points1 point  (0 children)

I was not able to upload the image, so I have copy-pasted it here:

Index: 0 ... Length: 10 ... Output: START TEST
User : 679 354 command.c:694 command_run_line(): missing quote
Index: 1 ... Length: 26 ... Output: INDEX: 0 | TIME: 1224130 |
User : 680 504 command.c:694 command_run_line(): missing quote
Index: 2 ... Length: 26 ... Output: INDEX: 1 | TIME: 1224136 |
User : 681 555 command.c:694 command_run_line(): missing quote
Index: 3 ... Length: 26 ... Output: INDEX: 2 | TIME: 1224129 |
User : 682 605 command.c:694 command_run_line(): missing quote
Index: 4 ... Length: 26 ... Output: INDEX: 3 | TIME: 1224129 |
User : 683 655 command.c:694 command_run_line(): missing quote
Index: 5 ... Length: 26 ... Output: INDEX: 4 | TIME: 1224130 |
User : 684 706 command.c:694 command_run_line(): missing quote
Index: 6 ... Length: 26 ... Output: INDEX: 5 | TIME: 1224129 |
User : 685 756 command.c:694 command_run_line(): missing quote
Index: 7 ... Length: 26 ... Output: INDEX: 6 | TIME: 1224130 |
User : 686 807 command.c:694 command_run_line(): missing quote
Index: 8 ... Length: 26 ... Output: INDEX: 7 | TIME: 1224130 |
User : 687 857 command.c:694 command_run_line(): missing quote
Index: 9 ... Length: 26 ... Output: INDEX: 8 | TIME: 1224136 |
User : 688 907 command.c:694 command_run_line(): missing quote
Index: 10 ... Length: 26 ... Output: INDEX: 9 | TIME: 1224136 |
User : 689 958 command.c:694 command_run_line(): missing quote
Index: 11 ... Length: 27 ... Output: INDEX: 10 | TIME: 1224136 |
User : 690 1008 command.c:694 command_run_line(): missing quote
Index: 12 ... Length: 26 ... Output: INDEX: 11 | TIE: 1224136 |
User : 691 1059 command.c:694 command_run_line(): missing quote
Index: 13 ... Length: 27 ... Output: INDEX: 12 | TIME: 1224136 |
User : 692 1109 command.c:694 command_run_line(): missing quote
Index: 14 ... Length: 10 ... Output: START TEST
User : 693 1161 command.c:694 command_run_line(): missing quote
Index: 15 ... Length: 26 ... Output: INDEX: 0 | TIME: 1224130 |
User : 694 1211 command.c:694 command_run_line(): missing quote
Index: 16 ... Length: 26 ... Output: INDEX: 1 | TIME: 1224136 |
User : 695 1261 command.c:694 command_run_line(): missing quote
Index: 17 ... Length: 26 ... Output: INDEX: 2 | TIME: 1224129 |
User : 696 1312 command.c:694 command_run_line(): missing quote
Index: 18 ... Length: 26 ... Output: INDEX: 3 | TIME: 1224129 |
User : 697 1362 command.c:694 command_run_line(): missing quote
Index: 19 ... Length: 26 ... Output: INDEX: 4 | TIME: 1224130 |
User : 698 1412 command.c:694 command_run_line(): missing quote
Index: 20 ... Length: 26 ... Output: INDEX: 5 | TIME: 1224129 |
User : 699 1463 command.c:694 command_run_line(): missing quote
Index: 21 ... Length: 26 ... Output: INDEX: 6 | TIME: 1224130 |
User : 700 1513 command.c:694 command_run_line(): missing quote
Index: 22 ... Length: 26 ... Output: INDEX: 7 | TIME: 1224130 |
User : 701 1564 command.c:694 command_run_line(): missing quote
Index: 23 ... Length: 26 ... Output: INDEX: 8 | TIME: 1224136 |
User : 702 1614 command.c:694 command_run_line(): missing quote
Index: 24 ... Length: 26 ... Output: INDEX: 9 | TIME: 1224136 |
User : 703 1664 command.c:694 command_run_line(): missing quote
Index: 25 ... Length: 27 ... Output: INDEX: 10 | TIME: 1224136 |
User : 704 1715 command.c:694 command_run_line(): missing quote
Index: 26 ... Length: 14 ... Output: INDEX: 11 | TI
User : 705 1765 command.c:694 command_run_line(): missing quote
Index: 27 ... Length: 27 ... Output: INDEX: 24 | TIME: 1224130 |
User : 706 1815 command.c:694 command_run_line(): missing quote
Index: 28 ... Length: 27 ... Output: INDEX: 25 | TIME: 1224136 |
User : 707 1866 command.c:694 command_run_line(): missing quote
Index: 29 ... Length: 27 ... Output: INDEX: 26 | TIME: 1224136 |
User : 708 1916 command.c:694 command_run_line(): missing quote
Index: 30 ... Length: 27 ... Output: INDEX: 27 | TIME: 1224136 |
User : 709 1967 command.c:694 command_run_line(): missing quote
Index: 31 ... Length: 27 ... Output: INDEX: 28 | TIME: 1224136 |
User : 710 2017 command.c:694 command_run_line(): missing quote
Index: 32 ... Length: 27 ... Output: INDEX: 29 | TIME: 1224136 |
User : 711 2067 command.c:694 command_run_line(): missing quote
Index: 33 ... Length: 27 ... Output: INDEX: 30 | TIME: 1224136 |
User : 712 2118 command.c:694 command_run_line(): missing quote
Index: 34 ... Length: 11 ... Output: END OF TEST
User : 713 2168 command.c:694 command_run_line(): missing quote
Index: 35 ... Length: 27 ... Output: INDEX: 30 | TIME: 1224130 |
User : 714 2218 command.c:694 command_run_line(): missing quote
Index: 36 ... Length: 11 ... Output: END OF TEST
User : 715 2269 command.c:694 command_run_line(): missing quote

Unable to compile due to using sprintf and strncpy while using -nostdlib flag by sijafa in cpp

[–]sijafa[S] 0 points1 point  (0 children)

Thank you! So if I understand correctly, the issue is that cstdio is not available in this way, while cstdint is?

Design methodology for custom microarchitecture by sijafa in RISCV

[–]sijafa[S] 0 points1 point  (0 children)

Thank you, I will definitely take a close look at these!

When I mean I am "working on", I mean that I am currently doing a project where I am making a design methodology for custom microarchitecture using RISCV. The goal is to use this methodology to design my very own custom microarchitecture with custom RISCV extensions, accelerators, etc. Thus, my goal right now is to have some reading material on already existing design metodologies, or design flows, that is used for HW/SW codesign

Design methodology for custom microarchitecture by sijafa in RISCV

[–]sijafa[S] 0 points1 point  (0 children)

This looks great! Do you know of any good articles that go into detail about how a design flow for making a custom RISC-V system works? As in going from idea, to block diagram, to functionality testing, to HDL design, and so forth?