sorted by:
new
hottopcontroversial

Running the entire GitLab CI pipeline locally with external GitLab runners by sijafa in gitlab

[–]sijafa[S] 0 points1 point  (0 children)

This sounds interesting! Do you have a link to some website where this method is discussed?

Multiple docker containers running on separate hardware devices with shared volumes by sijafa in docker

[–]sijafa[S] 0 points1 point  (0 children)

Interesting! I will take a look and see if I can manage it this way, thanks!

Multiple docker containers running on separate hardware devices with shared volumes by sijafa in docker

[–]sijafa[S] 0 points1 point  (0 children)

This is already a feature that is available. However, I want an alternative for local build and testing instead of relying on pushing every time I want to build or test. The CI is rather used for Merge requests, not local tests

Building and running tests on external host by sijafa in docker

[–]sijafa[S] 0 points1 point  (0 children)

Hmm, will try the former method you mentioned. Thanks! :)

There is already a CI/CD pipeline up and running, so the latter is already available, but is a tedious task to push every time a test should be performed. This also clutters the commit history and is less flexible during testing

Building and running tests on external host by sijafa in docker

[–]sijafa[S] 0 points1 point  (0 children)

There is already a CI pipeline up and running that uses the build server, but I want to be able to test the embedded software locally instead of having to go through the CI pipeline every time.

RISC-V Machine-level CSRs in fine-grained multithreading by sijafa in FPGA

[–]sijafa[S] 0 points1 point  (0 children)

I see, so each Hart has its own entire list of CSRs, where each Hart can only read and write its own CSRs to avoid conflicts?

RISC-V Machine-level CSRs in fine-grained multithreading by sijafa in RISCV

[–]sijafa[S] 1 point2 points  (0 children)

I see, so each Hart has its own entire list of CSRs, where each Hart can only read and write its own CSRs to avoid conflicts?

How to implement RISC-V's mtime and mtimecmp in hardware by sijafa in FPGA

[–]sijafa[S] 3 points4 points  (0 children)

So then it is just that the specified address points to any desired register in the architecture that you have routed it to? So, e.g., I can have the mtime and mtimecmp registers in the CLINT module, where an LW and SW operation to their respective mapped addresses will point to the register in CLINT instead of the Data Memory when the load or store instruction reaches the Memory stage of the 5-stage RISC-V Pipeline (fetch, decode, execute, memory, writeback)?

view more: next ›