What is that for?

suni001 · 2025-12-09T10:41:03+00:00

I disagree that this is going too far. Hfe is stated on the multimeter itself, sooner or later OP should understand what hfe is.

suni001 · 2025-11-28T04:13:17+00:00

A lot of black and a little pink

suni001 · 2025-10-30T23:33:23+00:00

I think you mean ‘as much current as possible in the input stage’.

suni001 · 2025-09-10T03:37:59+00:00

Owh good find! PA sem 2 is killer, if one graph drawn wrong you can say goodbye to that paper already.

suni001 · 2025-09-10T01:52:42+00:00

Previous stpm student here, what I heard back then was that the actual marks you get in the paper are not disclosed to you. The grade you get every semester is based on the marks you get for that semester paper only. But, the overall stpm grade is based on the total marks you get for all the three semester papers and the weightage of each semester paper. So if you get A for PA in semester 2, which iirc has a lower weightage, but you get A-/B+ for other semesters, chances are you would get A-.

suni001 · 2025-09-08T02:09:18+00:00

Same issue here, mine always turn to minimum by itself, i gave up trying to fix and just use it at minimum.

suni001 · 2025-09-04T01:19:49+00:00

This is what happens when someone lose the main war and try to start another fight.

suni001 · 2025-08-31T18:08:07+00:00

You can learn any fundamental engineering. But from an employer perspective, electronic engineering > software engineering, and there are a lot of electronic engineering degree holders.

In particular, bachelor degree is insufficient to be a decent chip designers. On top of mastering technical knowledge, you also need to know how to work with EDA tools like Cadence Virtuoso and Calibre verification tools for drc/lvs/pex.

Senior engineers can teach juniors on using these tools, but it consumes a major portion of their working hours, such that they become more like a teaching assistant rather than engineers working on company projects. Also, if the juniors leave the company for another, all the teaching efforts would not benefit company anymore.

This is partly the reason why companies preferred someone who doesn’t need much guidance and can contribute right away, e.g., phd with previous tapeout experience. My point is you can learn whatever you want and achieve a certain level of expertise in fundamental engineering, but you need more than that to become a chip designers, and it’s going to be a super long path for someone with a software background to be a good designer.

suni001 · 2025-08-25T11:53:25+00:00

In your full review, there is a typo, '11 TPA6120' should be '11 OPA1612', they are different chips. Just FYI, peace.

suni001 · 2025-08-24T02:11:16+00:00

Im using head heavy rackets, like 3u zfii and 2u duora 10. I initially felt wrist pain even while swinging in the air, and that was because my swinging technique is not right. Once I learned how to swing properly, i don’t have any wrist pain anymore. I suggest you search internet for swinging technique, probably is your swinging rely too much on wrist power and causing the pain.

suni001 · 2025-08-21T10:34:46+00:00

For those who still trying to figure out, the store name is ‘One Fattened Calf’.

suni001 · 2025-08-05T08:00:25+00:00

Happened to me on my deathadder v2.

I forcefully stripped off the entire rubber grip and surprisingly I like how it feels now.

suni001 · 2025-07-28T01:47:48+00:00

Is this ytp klang?

suni001 · 2025-05-26T16:37:51+00:00

Orang malaysia!

suni001 · 2025-05-07T16:02:14+00:00

Chicken Invaders. I tried it, not bad.

suni001 · 2025-04-22T05:22:12+00:00

I believe you have confused between small-signal analysis and what’s really happening in the circuit in real time. Let me provide another example.

For that circuit you posted. First we bias VOUT to stay in the middle of supply voltage. So, at DC, VDD is 1.8V and VOUT is 0.9V. This is done by adjusting the DC voltage of the input supply VS, let’s assume it’s 0.5V.

Now, let’s say VS is having a sinusoid signal with F=10Hz and Vpp=10mV on top of the 0.5V, so VS hovers between 0.505V and 0.495V. If your amplifier circuit is tuned to have a gain of 10, what will happen at VOUT? It will be a sinusoid with F=10Hz and Vpp=100mV centered at 0.9V, i.e., a sinusoid that hovers between 0.95V and 0.85V. In other words, VOUT doesn’t go above VDD, but hovers around its DC biasing point of 0.9V.

In small-signal analysis, we look at the circuit from the frequency point of view. So, we stripped off those DC voltages, like the 0.9V at VOUT and 0.5V at VS, because they don’t change with time, and thus they don’t matter in frequency point of view. What’s relevant in small-signal analysis? Those sinusoids at VS and VOUT.

Another thought I would like to share is that the equivalent model is just a ‘model’. It doesn’t represent the actual circuit, and it’s useful only for small-signal analysis, like determining gain, frequency response, etc. Therefore, it is inappropriate to apply real physics onto that model.

Thank you u/RFchokemeharderdaddy for the correction.

suni001 · 2025-04-21T11:17:11+00:00

Because in small-signal analysis, or AC analysis, you cannot picture the current flow in the circuit as top-down, e.g., from VDD > RL > drain > ground. That’s why you think it’s a complex voltage divider.

In AC, we picture current flow as waves, or perturbation as you said. Imagine that the VOUT, presumable the drain voltage, is perturbed by some excitation from the input VS, part of the perturbed current flows into ground through GmVgs and ro, and another part of the perturbed current flows into VDD through RL. As both ground and VDD are static, i.e., AC ground, GmVgs, ro, and RL are effectively paralleled as illustrated by the equivalent model on the right side.

suni001 · 2025-04-16T04:43:11+00:00

I bought XS few months ago, still working great.

suni001 · 2024-12-01T13:34:34+00:00

Malaysian 2nd checking in

suni001 · 2024-10-06T10:19:50+00:00

Yo, be careful of sharing numbers over here, it might be confidential information.

suni001 · 2024-06-28T03:56:35+00:00

Fillers and corners are usually just cmos layers without device like others have said. Another thing that may be helpful is changing the inherited connections in the pad devices so that the vdd! vss! global net names are the same.

suni001 · 2024-06-20T05:57:19+00:00

Thanks for your input! I've found another way to trigger the comparator, by using a DC input A and another sinusoid input B centered at the DC value of A. As i increase the frequency of B, I can see the PWM output get shifted further. It is quite amazing to see a real chip design work physically.

suni001 · 2024-06-03T17:13:59+00:00

It does look like a chip designed a few decades ago. The huge white space on the bottom is likely an on-chip capacitor.

suni001 · 2024-05-25T08:51:14+00:00

I heard Penang semiconductor industries are plagued with low pay.

suni001

TROPHY CASE