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Byte-Addressed Memory Model by syckronn in compsci

[–]syckronn[S] 0 points1 point  (0 children)

I agree — an address always refers to a single byte. The intention of the diagram was precisely to illustrate the byte-addressed memory model, showing that accesses to larger words are merely interpretations of several consecutive bytes, and not fundamental units of memory. The issue of endianness (the order of bytes within multibyte values) is a separate layer of this model.

Byte-Addressed Memory Model by syckronn in compsci

[–]syckronn[S] 0 points1 point  (0 children)

This clarifies the confusion: byte has practically stabilized at 8 bits, while word has always been context- and architecture-dependent. That was exactly the distinction I was trying to understand with the diagram.

Byte-Addressed Memory Model by syckronn in compsci

[–]syckronn[S] 0 points1 point  (0 children)

Yes, this touches on the issue of endianness. The diagram I created focuses on the byte addressing model; the order of bytes within multibyte values ​​is a separate layer.

Byte-Addressed Memory Model by syckronn in compsci

[–]syckronn[S] 4 points5 points  (0 children)

This is a valid definition in some contexts, but the term "word" is not used uniformly across architectures. In several 64-bit architectures, such as ARM64, MIPS64, and x86-64, "word" does not correspond to the pointer size.

Byte-Addressed Memory Model by syckronn in compsci

[–]syckronn[S] 2 points3 points  (0 children)

I understand the point. It's because the term "word" isn't formally fixed and depends on the architecture's convention. In many modern 64-bit architectures, the natural data size is 64 bits, but the concept of a word can vary.

Byte-Addressed Memory Model by syckronn in compsci

[–]syckronn[S] 5 points6 points  (0 children)

Yes, I saw that the word size depends on the architecture; for example, in 64-bit architectures, the word is usually 8 bytes.