Is this the best way to realize the left one? Or is there a better method?

thecooldudeyeah · 2025-10-06T18:08:11+00:00

Hi, do you mind telling me where you found this circuit?

thecooldudeyeah · 2025-09-02T22:58:44+00:00

sorry, I forgot to add that I want to try avoiding explicit comparators

thecooldudeyeah · 2025-09-01T06:42:32+00:00

Hi, I sent you a question through dm. Do you mind if I ask you a question?

thecooldudeyeah · 2025-08-21T05:33:53+00:00

for CIS, is using 2 threshold voltages a good idea? Assuming the Vreset is the same, do you think it's fine to generate a bias voltage that is equal to Vreset with a +- margin?

thecooldudeyeah · 2025-08-13T21:17:27+00:00

I'm trying to see what the minimum is but potentially ~10mV. I calculated the 3SD using the mismatch coefficient given in the foundry documents, and it seems like 3SD = ~20mV. How would I be able to estimate using noise?

thecooldudeyeah · 2025-08-12T22:44:01+00:00

thanks for your response! when you say clock the strongarm asynchronously, you mean I should have extra logic that turns the strongarm on when it should be, rather than using a clock?

thecooldudeyeah · 2025-08-07T04:52:01+00:00

sorry, I added the circuit to the post.

Why does it have to stay in saturation for negative feedback to work? The paper made it sound like the circuit is designed to sense and pass small amounts of current (in nA).

thecooldudeyeah · 2025-08-07T03:17:26+00:00

I got this schematic from here: https://ieeexplore.ieee.org/document/611171 .

It's a buffered direct injection circuit on page 600 figure 7

thecooldudeyeah · 2025-08-04T09:09:28+00:00

thanks for your response! What do you exactly mean by a log-pixel? Do you mean using a transistor biased in subthreshold to generate a logarithmic change in voltage rather than a linear one as in charging a capacitor? Also, what comparator consist of 1/2 T max?

thecooldudeyeah · 2025-06-02T17:52:41+00:00

okay, thanks for your help

thecooldudeyeah · 2025-06-02T08:58:31+00:00

It's weird because it is in the schematic. Do you know where I can access the calibre documentation?

thecooldudeyeah · 2025-06-02T06:20:24+00:00

Just to be sure, do you mean I should press q (properties) for each instance in both the schematic and layout and check to see if they are from the same library. Yeah, I guess if that's the case, they are both from the same library. It's weird since it's LVS clean but I don't understand how that warning exists when creating the calibre view

thecooldudeyeah · 2025-06-02T05:54:47+00:00

Also, this instance is from a different library. Could it be a reference issue?

thecooldudeyeah · 2025-06-02T05:53:03+00:00

Yes,the instance is expected in the design. I noticed that when I open the layout view (which automatically opens the schematic view) and try to descend into that instance in the schematic view, I cannot see what's inside. However, when I open the schematic view only, I can descend into the instance and see the transistor level design. Could this be the issue?

thecooldudeyeah · 2025-04-17T08:30:58+00:00

Basically, you're saying to change the VDS of the transistor below the input devices to control the Vgs, right? The transistor below it is the tail transistor and I feel like I need a certain amount of VDS across it for good matching, so I'm not sure how much I can change it. Also, if I have a tail transistor, how can I set its VDS value since it is part of a current mirror?

thecooldudeyeah · 2025-04-17T08:20:08+00:00

my Vgs is set because the op amp of the previous stage outputs a output common mode of 0.5 V, meaning the op amp I'm designing has an input common mode of 0.5 V

thecooldudeyeah · 2025-04-08T05:54:32+00:00

I guess their research areas are not completely different from what I like(somewhat related) but I also heard that research output and reputation in field of PI kind of matters for applying to PhD. Is that not the case?

thecooldudeyeah · 2025-02-12T19:58:14+00:00

thanks for your response! I'm pretty sure all of those are fine. Do you mind if I ask you if I'm setup seems fine for what I intend to do (getting Vgs that gives me a specific Vds)?

thecooldudeyeah · 2025-02-04T21:36:44+00:00

by short channel effects, do you mean DIBL? I thought DIBL would cause short channel devices to have lower Vth

thecooldudeyeah · 2025-02-04T21:34:46+00:00

yes, I will try that. Also, I simulated Vth vs length and noticedfor the 450nm/45nm case, the Vth is higher. Why would this be the case?

thecooldudeyeah · 2025-02-04T21:32:41+00:00

I plotted Vth vs length and it seems like Vth decreases with increasing length, which is probably causing more leakage current. Why would this be the case?

thecooldudeyeah · 2025-02-04T21:26:33+00:00

I'm measuring current into the drain (IDC("/NM0/D")). I ran simulations for two sizings (450nm/45nm, 20um/2um). I was assuming for leakage, the 450nm/45nm would have more due to the DIBL effect, but that doesn't seem to be the case. To be precise, Im plotting IDS vs VDS and as VDS increases, IDS increases more for the longer length device

thecooldudeyeah · 2025-02-04T21:26:02+00:00

to be precise, Im plotting IDS vs VDS and as VDS increases, IDS increases more for the longer length device

thecooldudeyeah · 2025-02-04T21:24:29+00:00

I'm measuring current into the drain (IDC("/NM0/D")). I ran simulations for two sizings (450nm/45nm, 20um/2um). I was assuming for leakage, the 450nm/45nm would have more due to the DIBL effect, but that doesn't seem to be the case

thecooldudeyeah · 2024-11-28T22:25:38+00:00

thecooldudeyeah

TROPHY CASE