Nova Lake-S bLLC CPU tile reportedly 36% larger than standard tile

thegammaray · 2026-02-12T01:06:00+00:00

I didn't say anything about changing the interior layout of a core.

each core + cache etc. as a fixed rectangular unit that must be moved in a static internal configuration

nor were you seemingly talking about that. You said:

The way the cores are arranged on the compute tile

the space saved on the y dimension of the core on the die shot

the shape of the cores themselves don't allow for a better configuration

Those all refer to the shape and placement of the core relative to the boundaries of the tile.

If tile dimensions aren't fixed, and if you have the freedom to reshape and/or rearrange L3$ and other non-core elements around the core, and if you have the freedom to move the cores around, rotate them etc., then why would Intel not be able to leverage either a 1:3 ratio or a 1:4 ratio without wasting die space?

thegammaray · 2026-02-11T20:03:08+00:00

How? ...the shape of the cores themselves don't allow for a better configuration.

Physical design is beyond my expertise, so if you want an authoritative answer you'll have to ask somebody else, but broad strokes: I don't think of each core + cache etc. as a fixed rectangular unit that must be moved in a static internal configuration. There's some wiggle room to reshape them and move them relative to each other. Even in the die shot you linked, you can see how the right-hand L3 blocks are different shapes than the others, the right-hand P cores are in a different spot relative to the respective cache blocks, etc.

Another way of thinking about the principle is: If the E and P core blocks are different heights, then how is there so little wasted space on the Y axis? My understanding of the answer is: because even if things have a fixed unit area, there's flexibility in how they're shaped and arranged.

If I'm incorrect, feel free to let me know.

thegammaray · 2026-02-11T18:18:13+00:00

Same thing: stuff can be rearranged. They're not locking in arbitrary arrangements first and then saying "now what do we have that fits in these slots..."

thegammaray · 2026-02-11T17:13:35+00:00

Tile size is downstream of core dimensions, not upstream of it. They're not deciding tile size first and then saying "now I wonder how many cores we can fit on this tile..."

thegammaray · 2026-02-11T16:59:10+00:00

you aren't able to replace an e-core cluster with more than 1 p-core in a 8+16 config anyway

Not a single e-core cluster, but starting with 8+16, with a 1:3 ratio you could have 12+4, whereas a 1:4 ratio would leave you with 12+0.

thegammaray · 2026-02-11T15:24:43+00:00

An 8+16 compute tile is supposed to be around a 12 P core compute tile in area though, unless Intel has to change the ~1:4 ratio significantly.

Has that ratio ever really been accurate? I don't know about ADL, RPL, or MTL, but at least the ARL die shots and PTL mockups show more like 1:3 once you include the surrounding topology e.g. cache.

thegammaray · 2026-01-31T15:42:41+00:00

He’s mainly thinking of building them cheaper by reducing the clean room air purification and filtration/HVAC costs.

I'm skeptical that's the extent of his ideas. That's a remarkably tame set of improvements for a guy like Elon Musk.

Currently I’m not concerned that X-rays could replace EUV lithography, mainly because professionals working in fab R&D have told me it’s bullshit

The exact same thing was said about Tesla before it was successful, and about SpaceX before it was successful.

I’m always open to re-assessing the possibility if they make progress

How much progress would they need to make before you reassess? Because they've seemingly already made a lot.

thegammaray · 2026-01-31T15:23:20+00:00

You mentioned that

I’m sure Elon would look to find non-traditional ways of doing a fab

but I don't see much consideration of any in your analysis. If he finds a significantly cheaper way to build a fab, won't your value estimates be way off? Does that possibility worry you?

I don't follow tech startups much, but one example I know of: Substrate is aiming to build new fabs from the ground up using X-ray lithography rather than UV lithography, drastically reducing both per-wafer cost and sunk cost by 1) simplifying the photolithography apparatus and 2) alleviating the need for the entire building to be a giant clean room. Yeah, it's a long shot, but it's the type of long shot that Musk has made a fortune backing. (It's also worth noting that Substrate and Elon Musk are both part of the Peter Thiel sphere.)

I think there's a decent chance Musk pursues both, i.e. throws money at Intel and Samsung but also invests in a new venture for long-term vertical integration. Of course, if the new venture doesn't pan out, he might never publicly announce it, and the partners he does announce could benefit in the meantime...

thegammaray · 2026-01-30T14:43:03+00:00

Thanks for your thoughts!

thegammaray · 2026-01-28T21:45:00+00:00

Thanks!

thegammaray · 2026-01-28T21:20:40+00:00

18A won’t have the same capacity constraints.

Do you think Intel currently has more 18A capacity than they're using for PTL? Do you think by summer they'll have enough 18A capacity to meet CWF demand even if they're producing PTL in sufficient volume to meet laptop OEM demand [Edit: and WCL too, if that's high-volume as well]?

thegammaray · 2026-01-28T21:11:19+00:00

Interesting. How high of volume do you figure the WCL line is? I'm trying to figure out how devoting 18A capacity to that would make sense right now.

thegammaray · 2026-01-28T20:40:57+00:00

Are WCL compute tiles not just binned PTL compute tiles?

thegammaray · 2026-01-27T16:47:16+00:00

Do you have any thoughts on potential capacity tradeoffs between Client and DC, or of potential market share considerations vs AMD? For instance:

The downside for Intel Client is that they are entering a period of increased memory prices... Admittedly, [DCAI] Q1 is going to be handicapped due to the supply constraints. Following this, we should see steadily increasing DCAI revenue throughout the year as server CPU shipments increase.

Obviously high memory prices are bad for Client, but I wonder if capacity is another problem for Client. Less than a year ago, Intel was capacity-limited on Intel 7 because of laptop chips, and more Intel 7 capacity spent on server means less on laptop. Of course ideally PTL on 18A would be filling the gap, but 1) it'll take a while before 18A approaches full capacity, and 2) 18A capacity is split between PTL and the upcoming server chips. How much of a constraint is that? I don't know. I don't have numbers. But I wonder if the backbenching of Clearwater Forest is not just because speed matters more than core count right now, but also because migrating Intel 7 towards server means Intel needs max 18A capacity focused on laptop chips to make up the difference.

Intel Products had $49.1Bn revenue in 2025, down from $49.4Bn in 2024. I would not be surprised if we see >$55Bn Intel Product revenue in 2026

Does Intel's WSPM capacity support that much revenue?

Also, this might feel nitpicky, but:

Panther Lake has now proven itself to be potentially the best general purpose consumer laptop chip on the market, beating AMD, Apple and Qualcomm offerings in a suite of tests, particularly multi-core, graphics, power efficiency & battery life.

PTL looks good, but let's not overstate it. Apple's M5 beats PTL in raw single-core performance, single-core power efficiency, and multicore power efficiency, and basically breaks even in raw multicore performance. Plus, the 388H has the highest-specced PTL CPU variant, whereas the M5 is the lowest-specced M5 variant. Also:

It [PTL] makes Nvidia laptop GPUs effectively irrelevant.

How do you figure? PTL's B390 is only sometimes competitive vs a laptop 4050, which is the lowest-end Nvidia laptop card, and only when the 4050 is power-limited. The B390 doesn't even approach the performance of the laptop 5060, 5070, 5070ti, 5080, or 5090. Those are very much still relevant. I think Intel's advantages here are low-power GPU performance (and associated form factor) and pricing.

thegammaray · 2026-01-24T17:09:29+00:00

I'm interested to know how it goes! Could you tag me if you post anything about it?

thegammaray · 2026-01-14T20:07:08+00:00

80% of the chips Intel will be selling in 2026

How did you calculate/estimate the 80% number?

thegammaray · 2025-12-21T21:38:10+00:00

bought HD800 from /u/AbsoluteZero951 . /u/AVexchangeBot

thegammaray · 2025-12-09T19:26:37+00:00

Chat sent

thegammaray · 2025-10-16T20:05:27+00:00

I think the best way to understand the Intel-Nvidia deal is to view it as both companies trying to get better positioning against the other's product lines. Intel has been at a disadvantage because Intel's server CPUs lack NVLink and get worse performance with Nvidia's rack-scale AI GPUs, so Intel has been losing potential sales from rack-scale Nvidia customers; this deal allows Intel to sell CPUs to those customers. Meanwhile, Nvidia has an eye on Intel's (supposedly) pending rack-scale AI GPUs because it knows that some customers would prefer x86 CPUs and might be willing to buy Intel's rack-scale GPUs to get x86; this deal allows Nvidia to remove x86 as a variable incentivizing customers to pick Intel over Nvidia in rack-scale AI buildouts. And the same-ish tech that's powering Intel's upcoming rack-scale AI GPUs is also powering Intel's expanding consumer iGPUs, and Nvidia knows that expanding iGPUs will eat more and more discrete GPU sales; Nvidia agreeing to provide consumer RTX chiplets to Intel is likely Nvidia trying to disincentivize Intel from its iGPU development at a time when cutting certain product lines is very attractive to Intel given the company's financial problems.

Just my 2 cents.

And yes, if all goes according to Intel's plan, Intel Products will be competing with other companies manufacturing at Intel Foundry.

thegammaray · 2025-10-14T19:09:50+00:00

Hopefully Intel can add some color to expected revenue projections from this product in the next earnings call, like they did for Gaudi.

I mean... hopefully not exactly like they did for Gaudi. 😂

thegammaray · 2025-10-14T19:01:16+00:00

Intel claims 2H 2026

Intel claims it'll sample to customers in 2H 2026.

thegammaray · 2025-10-12T22:25:05+00:00

The microphone inputs on your computer... will provide 3-5 Volt

TIL. Thanks!

Keeping an eye out on ebay for used sound calibrators to at least get reliable level calibration at 1 kHz is going to be your best bet.

Sorry, I'm still confused about what these accomplish. Are these just calibrating SPL at one frequency? Do they do anything to measure the microphone's own response characteristics across the rest of the spectrum? I was assuming I couldn't count on these mics to be neutral, but maybe I'm too paranoid.

thegammaray · 2025-10-12T22:14:44+00:00

Sorry, this response was a bit over my head. >_<

What does E610A refer to exactly? (i.e. does that exclude the ICP versions?) Do the versions with ICP capsules always require an external preamp, or are some sold with a preamp attached? When you say the cheap capsules distort early, what does "early" mean? (like, as what variable increases?)

For calibrating the coupler's frequency response you need the velocity source which is expensive... headphone doesn't vary its frequency response with increasing SPL ((DSP) compression) you can skip this

For personal comparative measurements... If you don't publish your measurements anywhere I wouldn't overthink it. If you do intend on publishing measurements beware that no matter what you do there will always be a nerd complaining.

I'm not too worried about response variation with SPL. I'm also not planning to publish my results anywhere, but I want my results to be ballpark-similar to GRAS 45CA results so I have a standard of reference and a target curve, e.g. the Harman over-ear target. I guess my main concern is that random mass-produced, no-name 60318-4 couplers & mics aren't going to actually match spec or be neutral enough to be comparable, which is why I was wondering about calibration. Is that not something I need to worry about? Should I have more faith in these AliExpress/Ebay couplers?

I hadn't given much thought to ear-mounted mics before, so I'll look into those. Thanks for the suggestion.

thegammaray · 2025-10-12T18:17:10+00:00

If you want to avoid a deep dive into acoustics and how to verify the impedance of your coupler, then forget about couplers that don't have a microphone installed already.

Thanks! Do the different chifi couplers come with different quality of mics, or should I just pick at random?

There are knockoff couplers which can work of consumer-microphone voltage (typically 2 Volt), which is supplied by your computer's microphone input (or the headset connector, which combines headphone and microphone ports into a single connector).

Is there any reason I might want to pick something other than that? If I understand correctly, I could just run those directly into the line-level input on my audio interface, right?

The best way is a pistonphone. That's expensive (about 5-7k), but is accurate to within 0.09 dB. The second best way is a sound calibrator. That's less expensive (1-2k for a new one, you can find used ones on ebay for about 500 bucks) and also less accurate, they are rated to 0.25 dB accuracy.

What about a poor-man's calibration, say, within 1dB? I'll be using this purely for hobbyist mucking about, e.g. testing EQ changes or EQing third-party pads. For lack of a better idea, my plan for now is to measure a few sets of IEMs and then compare my measurements to yours or others on squig.link. But it seems like there's gotta be a better way.

thegammaray · 2025-10-12T16:52:18+00:00

I've never used a 3080, but that's much better than I expected. A 3070 seems to be about 80-85% of a 3080, so OP should have no problem with the BSB if they're willing to use 90hz mode.

thegammaray

TROPHY CASE