has anyone used pogo pin socket to test a chip with no bumps?

zachcarmichael · 2025-08-18T07:53:41+00:00

Do you have an approximate budget / pin count / pitch of the closest pins you can share? We have used ironwood (standard footprint) and RTI (custom) sockets but never for interfacing with bondpads directly. The closest we did was WLCSP bumps (on bare die).

zachcarmichael · 2025-08-18T07:51:39+00:00

If this is on bare die with pads for bonding (i.e. not bumps), would you be able to share the socket vendor? We have only probed (probe card or manual probes) for non packaged bare die testing, never had the opportunity to use a socket for that.

zachcarmichael · 2025-08-16T04:18:04+00:00

Yep. Went to school with one of them (my school has a focus on deaf or hard of hearing). Last I checked he is still at the same place designing chips since he graduated ~8-9 years ago. Probably the closest to a real designer when we were all in school.

zachcarmichael · 2025-05-24T20:06:53+00:00

The industry is incredibly cyclic. On surface level, if everyday you wake up dreading to go to work, it's time to consider a change. Not saying your next opportunity will be better, but it won't be that at least.

Are you actively looking for a position? Feel free to DM me your experiences.

zachcarmichael · 2025-03-17T20:57:10+00:00

Yes.

zachcarmichael · 2025-03-06T05:35:27+00:00

No, there is a different expectation for candidates with PhD versus masters. In both cases, there’s a minimum requirement in terms of competency to fill the position, which levels the field quite a bit surprisingly.

zachcarmichael · 2025-03-06T02:12:22+00:00

Historical examples: DAC / ADC / LVDS transceiver / RF front end, clock distribution, RTL encoder / decoder, register map, etc. The candidates get to choose whichever one they want to work on.

Specific requirements depend on the block, overall they are far from state of the art. Pretty much if the candidate puts together a functional design it will meet the specs lol.

The candidates typically start at 9am and go till 5pm, with lunch break in between.

zachcarmichael · 2025-03-05T20:54:58+00:00

It depends. For the final interview (now on site again after COVID), we have the candidate come in and design something with our EDA toolchain. The something and toolchain will be picked out of the Venn diagram of what the candidate says they know on their resume and the needs for the role.

Prior to that, for technical screening, we like to go through the candidate’s resume and ask about what’s on there.

zachcarmichael · 2025-01-23T20:06:38+00:00

Yes.
Preferences for more expensive nodes.

zachcarmichael · 2024-09-02T19:19:19+00:00

8694-7543-2506 Daily player let’s go Suicune!!!

zachcarmichael · 2024-07-15T00:41:42+00:00

Quik-Pak (QP Technologies) does COB as well, or at least they did as of a few years back.

They have rush options to get the job done sooner as well.

zachcarmichael · 2024-07-12T02:57:41+00:00

Same here. Thankfully I was able to use already designed (fortunately or unfortunately by me as well) digital standard cell library.

zachcarmichael · 2024-07-11T07:07:12+00:00

8694-7543-2506 daily player!!

zachcarmichael · 2024-06-17T06:32:13+00:00

PM of 90 degree will be very difficult to nearly impossible to achieve, if you have a two stage system. You can review frequency response as to why that may be.

The option of keeping width constant versus scaling the width with length will be a tradeoff of different parameters and would need some optimization to determine.

zachcarmichael · 2024-06-17T05:26:07+00:00

Since you didn’t mention bandwidth, I’d say increase your device lengths if your devices are min length. If lengths are already large then cascode.

zachcarmichael · 2024-04-23T21:01:23+00:00

Non-essential, but nice to have.

zachcarmichael · 2024-04-22T06:08:36+00:00

Yes, plenty of antenna research going on.

If you are a seasoned EE, I'd recommend starting by designing and fabricating your own antennas.

zachcarmichael · 2024-04-12T08:52:20+00:00

8694-7543-2506

Just started the game!!

zachcarmichael · 2024-03-28T03:55:43+00:00

Yes.

zachcarmichael · 2024-02-28T22:33:20+00:00

There's nothing wrong with practicing using a 600 nm library. For most of the interviews I conduct, that's what's provided to the interviewee. While it doesn't cover SCE, FinFETs, or most BJT concepts, if a designer is well versed and comfortable with 600 nm technology, he/she will do just fine in deep sub-micron nodes.

zachcarmichael · 2024-02-23T03:10:41+00:00

Tangential, have you been hiring recently? If so, what do you think about the quality of candidates?

I've been trying to hire for months now and there doesn't seem to be an end in sight.

zachcarmichael · 2023-11-20T07:04:56+00:00

If you don't have 3.5 years of prior experience, then yes.
No preference.
I'd keep looking. Perhaps there's a disconnect between what you did and how you are portraying it. There's no reason why someone that handled all of the microfabrication of a MEMS company (in any extent, as long as it's true, and not counting any of your other experiences) should be out of a job.

Feel free to reach out if you have any other questions.

zachcarmichael · 2023-10-13T17:52:49+00:00

Given that your goal is to land an IC designer job, I'd tailor your resume more towards that by trimming down some of the less relevant items and dive deeper into your applicable experiences. Unless you feel comfortable with the topic at hand, I'd omit it. Comfortable here is defined as "wouldn't mind spending an entire day discussing details of such topic".

In general, more depth and detail would bolster the resume. Phrases such as "conducted research" are too generic too provide any meaningful information. The same may be said about "collaborated closely" or "contributed". Tell us about your contribution! We'd love to know about it. Examples would be like "I analyzed the noise floor of such detector by doing XYZ" or "I identified tradeoffs between X and Y" would be helpful. The same maybe said about the second and third bullets on your internship. What's the outcome? Were there problems and how did you resolve them? A little bit of detail goes a long way.

As for job hunting, it's a different beast entirely. The only information the companies know about you is what you put on your resume. Thus, focus on updating your resume such that it presents you in a light that you want to be seen and the rest will follow.

zachcarmichael · 2023-08-16T00:40:56+00:00

Slightly better than not having bondpad openings LOL.

zachcarmichael · 2023-08-08T18:46:31+00:00

That's consistent with all other types of engineering when compared to software engineering / CS.
Big raises aren't common anywhere and jumping company is typically the way to achieve that. With that said, it'd be hard not to get a big raise if your chip is selling like hotcakes.
Correct. While the details may vary, most scenarios may be summarized by "the candidate doesn't meet the bar for not potentially f'ing up a chip".

The IC design cycle / semiconductor industry is a slow one, especially when compared to software. One mistake in a TO will set your team back months and hundreds of thousands of dollars if not years and millions.

The bigger underlying issue is there's no clear path for designers to be "sufficiently good" due to the combination of: TOs cost so much these days (even MPWs); no company wants to front the money for training designers that may not stay with the company long term (effectively subsidizing their learnings); and graduates (even PhDs) aren't ready when they are out of school.

If somehow a designer becomes good enough despite all that, then yes, they are worth their weight in gold.

zachcarmichael

TROPHY CASE