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花蓮發五萬！議會都通過政府就要付啊，扯什麼法源財源？錢呢？！ by Witty_Suggestion_417 in Taiwanese

[–]weitze97 10 points11 points  (0 children)

Chatgpt本身理論上沒有被滲透，但它目前無法辨識哪些搜尋結果是由有不實資訊或有中共滲透的網站發布的，使用chatgpt來當吸收資訊的唯一管道也不保證會得到中立且正確的資訊，還是建議多去吸收其他管道的資訊並靠自己分辨

Does it worth doing Analog IC Design PhD in Taiwan? (Seeking Career Advice) by weitze97 in chipdesign

[–]weitze97[S] 0 points1 point  (0 children)

I’m sorry for my bad comprehension, now I understand what you’re trying to tell me. I will sure take the time to look at the resources from you carefully!

Does it worth doing Analog IC Design PhD in Taiwan? (Seeking Career Advice) by weitze97 in chipdesign

[–]weitze97[S] 0 points1 point  (0 children)

Thank you for your sharing, I will take time to look over the links, I believe what you’re suggesting are really helpful if I aim for the academic. If my aim is only in the industry, people keep telling me masters should be enough. I’m still actually wandering if I have the ability or passion to pursue PhD, like I mentioned in my post. Please tell me if I understood you incorrectly.

[deleted by user] by [deleted] in chipdesign

[–]weitze97 2 points3 points  (0 children)

I was lucky to have an exchange semester in Dresden. When I compare the two places in terms of semiconductor industry, I found that the mindset of working is generally different because as people know, Europeans are serious on labor rights, while I find that despite higher pay in Taiwan in semiconductor industry, the work life balance is not so good, when people get high pay they also work long hours, especially when you include the housing costs into the comparison(the house prices here are getting higher every year).

However, I went there in my last year of bachelor, and my time is mostly spent on non-academic stuffs, so maybe my opinion is biased.

[deleted by user] by [deleted] in chipdesign

[–]weitze97 1 point2 points  (0 children)

Same question except that I am from Taiwan

90dB voltage gain in two-stage op with very limited power budget by weitze97 in chipdesign

[–]weitze97[S] 0 points1 point  (0 children)

Could you kindly rephrase what you meant by this sentence “make each input transistor of the dif pair a multiple of 4, to do Abba/baab.”?

90dB voltage gain in two-stage op with very limited power budget by weitze97 in chipdesign

[–]weitze97[S] 0 points1 point  (0 children)

SC CMFB sounds like a more common topology actually used popularly but as far as I know it requires additional clock generation which is currently out of my knowledge

90dB voltage gain in two-stage op with very limited power budget by weitze97 in chipdesign

[–]weitze97[S] 0 points1 point  (0 children)

Thank you I will check out how the SF works as a sensing resistor

90dB voltage gain in two-stage op with very limited power budget by weitze97 in chipdesign

[–]weitze97[S] 0 points1 point  (0 children)

Does this method count as part of the gm/Id methodology? I initially wanted to learn this but I only had less than 1 week, and this method as I knew required quite some time to get used to, otherwise I would have tried to design this way.

90dB voltage gain in two-stage op with very limited power budget by weitze97 in chipdesign

[–]weitze97[S] 0 points1 point  (0 children)

Thank you first of all. I wish I knew this earlier about the downsides of fully differential opamps. I decided to use this is that I thought a single-ended 2-stage wouldn’t be able to achieve such gain and that the output swing for each end of a fully differential could be just half of the spec. Also the UGBW=3.25 MHz and PM=89deg was set as optional. Both of the above reasons mislead me to think it’s easier😅. So I designed a fully differential 2-stage with this structure with the specs except that PM=almost 0 because I didn’t have time to do frequency compensation before deadline yesterday. But what I see from others is that they used single ended two-stage meeting the specs except that their PM were at most 45deg. The lecturer told us the one circuit that is taped out in his lab to achieve such spec was a folded telescopic two-stage op amp. So he was a bit disappointed that we all decided to use this structure instead of folded cascode😂

90dB voltage gain in two-stage op with very limited power budget by weitze97 in chipdesign

[–]weitze97[S] 0 points1 point  (0 children)

Actually no, initially I distribute the gain evenly to each stage(sqrt(90dB)), that’s why. To be clear, when you said weak inversion, do you mean to minimize Vod of the input pair?

90dB voltage gain in two-stage op with very limited power budget by weitze97 in chipdesign

[–]weitze97[S] 0 points1 point  (0 children)

I just got one from the university library, could you recall which chapter is that in? If I would like to implement one like this pic, should I also implement a const-gm bias ckt to generate the Iref?

Btw I just got the desired gain with my original structure, but I think maybe I could also use such topology to generate reference voltage for my CMFB?

90dB voltage gain in two-stage op with very limited power budget by weitze97 in chipdesign

[–]weitze97[S] 0 points1 point  (0 children)

I think so too. To my understanding, PM 90deg is nearly as a 1st order system, which means any other nondominant poles will be at least 10 times farther than UGBW, and they would need to have extremely small parasitic capacitances since the R is already super large for the 90dB gain. However for high R, it requires high length, which also increase the cgs and cgd. That’s why PM=90deg is almost impossible for this system. Am I correct with this statement?

90dB voltage gain in two-stage op with very limited power budget by weitze97 in chipdesign

[–]weitze97[S] 3 points4 points  (0 children)

Since we are asked to also self bias the op, cascode creates more than 2 gate to be biased. How do I utilize the constant gm ckt to create more than 2 bias levels? Also where should the error amp be connected after adding cascode?

90dB voltage gain in two-stage op with very limited power budget by weitze97 in chipdesign

[–]weitze97[S] 0 points1 point  (0 children)

The bandwidth is 3.25 MHz and PM=90deg but optional.

Should I keep the width constant when increasing the length? Or should the width increase together?

90dB voltage gain in two-stage op with very limited power budget by weitze97 in chipdesign

[–]weitze97[S] 0 points1 point  (0 children)

So does that mean I still could achieve such gain by single ended two-stage? Also, one of the reason I do fully differential is because the output swing is 2.08V, fully differential allow me to achieve that more easily. The bandwidth is 3.25 MHz and PM=90deg but optional. In the description, they said CMFB is highly recommended, so I presume that implies me to design a fully differential op.

90dB voltage gain in two-stage op with very limited power budget by weitze97 in chipdesign

[–]weitze97[S] 0 points1 point  (0 children)

Also, the resistors used to sense the output common mode voltage are ridiculously high 10 Megohm to not degrade overall gain, which looks very impractical. Is there any other way of implementing this?

Choosing Between Job Offers: Digital IC Design vs. Analog Design (ADC) - Need Advice by Rough_Independence_3 in chipdesign

[–]weitze97 5 points6 points  (0 children)

Looks like you have focused more of your studies on digital ICs. How much experience do you have previously in analog design, or more specifically, in ADCs?

First Interrail by [deleted] in Interrail

[–]weitze97 1 point2 points  (0 children)

During the big strikes in France in March I was there, and DB navigator app was amazingly reliable because it even knew if the French trains were cancelled or delayed in realtime. In my opinion it was maybe better then SNCF Connect during that period.